BOM data fix J1 MPN

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andsai

BOM data fix only, no layout or schematic changes.
J1 (5 V input, Molex Nano-Fit 2 pin): the footprint is 1053131202 (gold) and that is the part we buy. The Manufacturer Part Number property of J1 still reads 1053131102 (tin). Set the MPN of J1 to 1053131202, manufacturer Molex, and make any related part description text say gold contacts. Do not move, re-route or replace anything else.
Then confirm the new BOM line for J1 and that DRC/ERC results are unchanged.

flux

I’ll capture the current BOM and DRC/ERC state, update only J1’s metadata, then re-run both checks to confirm there is no design delta.

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J1’s purchasing metadata is corrected in place. I’m now verifying the generated BOM line and comparing fresh DRC/ERC results against the pre-change counts.

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Updated J1 BOM metadata only:
  • MPN: 1053131202
  • Manufacturer: Molex
  • Description/type: Wire-to-board / wire-to-wire connector, gold contacts
  • Footprint: CONN-TH_2P-P2.50_MOLEX_1053131202
  • Quantity: 1
No component replacement, connectivity, schematic geometry, routing, placement, or layout changes were made.
Fresh checks confirm results are unchanged: DRC remains at 18 errors and 35 warnings; ERC has no reported findings.
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Schematic

Layout

3D View

Independent Block 6 Review
Scope: U15–U18, R50–R64, C40–C44 and direct interfaces to U14 / later connector placeholders. Review result: completed with two localized metadata corrections, one electrical-margin correction, and the trigger startup-safety pull-up added.
Corrections made
  • U17 property corrected/clarified: MCLK_BUF_EN = 0 makes all four 5PB1104 outputs logic low, not high-Z.
  • U16 property corrected: classified as the enable inverter rather than a level translator; its description now states that the high-Z guarantee applies after the 1V8 logic rail is valid.
  • R63 changed from 100kΩ to 47kΩ. At U17's specified 5uA maximum input leakage, 100kΩ had only about 8mV worst-case low-level margin including 1% tolerance at VDD=1.71V. 47kΩ limits the resulting bias to about 0.237V and adds at most about 38.7uA DC load at 1.8V.
  • R64 added: 100kΩ, 1%, 0603 pull-up from TRIG_OE_N to 1V8. Its role metadata identifies it as the direct startup-safety bias that holds all four U15 active-low OE inputs disabled before U16's output is guaranteed.
Parts, power and decoupling

Table

RefExact part / value1V8 and groundLocal bypass
U15SN74LV4T125RGYRVCC→1V8; pins 7 and exposed-pad pin 15→GNDC40 100nF
U16SN74LVC1G04DCKRVCC→1V8; GND→GNDC41 100nF
U175PB1104PGGK8VDD→1V8; GND→GNDC42 100nF + C43 1uF
U18DSC1001DI2-037.1250, DNPVDD→1V8; GND→GNDC44 10nF
R64 is a generic 100kΩ ±1% resistor in SMD_0603_1608Metric, connected directly between 1V8 and TRIG_OE_N.
U15 operates from 1.6–5.5V and its input recommended range is 0–5.5V even with VCC=1.8V, so expected 1.8V, 3.3V and 5V service-trigger levels are voltage-tolerant. Its guaranteed 1.65–1.9V input thresholds are VIH ≥1.0V and VIL ≤0.5V over −40°C to 125°C. U15 output amplitude is set by its 1.8V VCC.
U17's 1.8V operating range is 1.71–1.89V. U18 is a CMOS oscillator supporting 1.8–3.3V operation; DI2 identifies 2.5×2.0mm QFN, −40°C to +85°C and ±25ppm, and 037.1250 is 37.125MHz.
Trigger path and enable behavior
  • TRIG_IN connects to all U15 A inputs and R54=100kΩ to GND. U15 A-input leakage is ±1uA maximum at valid rail levels, so the worst bias error is about 0.101V including resistor tolerance, comfortably below VIL=0.5V.
  • TRIG_BUF_EN is U14:P13, R49=100kΩ to GND and U16:A. After 1V8 is valid, low input makes U16:Y high; TRIG_OE_N then reaches all four U15 pins ~1OE, ~2OE, ~3OE, ~4OE.
  • U15 OE is active-low: OE low passes A to Y; OE high makes Y high-Z.
  • Startup safety closed: R64 directly pulls TRIG_OE_N high as 1V8 rises, independently biasing all four U15 OE inputs toward their disabled/high-Z state before U16's output is guaranteed. U15's function table confirms OE high produces Y=Z.
  • U16 low-drive impact: when TRIG_BUF_EN is asserted, U16 sinks only 1.8V / 100kΩ = 18uA through R64 (18.2uA worst case at 1.8V with −1% resistor tolerance). This is just 0.46% of U16's guaranteed 4mA recommended sink capability at VCC=1.65V; U16 guarantees VOL≤0.45V at 4mA. Therefore R64 does not compromise U16's asserted-low drive.
  • Output mapping is exact and without cross-connections: U15 1Y→R50→CAM1_XTRIG; 2Y→R51→CAM2_XTRIG; 3Y→R52→CAM3_XTRIG; 4Y→R53→CAM4_XTRIG. R50–R53 are all 33Ω.
MCLK fan-out and source selection
  • U17 1G is active-high. MCLK_BUF_EN=1 passes CLKIN; MCLK_BUF_EN=0 forces every Yn low, not high-Z.
  • R48=100kΩ pulls MCLK_BUF_EN low at startup, so the fitted-default camera MCLK outputs are low.
  • Exact output mapping: Y0→R55→CAM1_MCLK; Y1→R56→CAM2_MCLK; Y2→R57→CAM3_MCLK; Y3→R58→CAM4_MCLK. R55–R58 are all 33Ω.
  • Source links are mutually exclusive population options:

Table

Selected sourceFitKeep DNPDefault metadata
On-board 37.125MHzU18 + R59R60, R61U18 and R59 excluded from BOM and PnP by default
Host clockR60R59, R61; U18 remains DNPR60 excluded from BOM and PnP by default
External clockR61R59, R60; U18 remains DNPR61 excluded from BOM and PnP by default
Shipping defaultnoneR59, R60, R61, U18no source contention; R63 biases MCLK_SRC low
U17 CLKIN accepts up to 3.465V absolute maximum, but its guaranteed logic thresholds track its 1.8V VDD (VIH ≥0.7×VDD, VIL ≤0.3×VDD). Therefore HOST/EXT clock sources must have valid 1.8V-compatible logic levels and must not exceed 3.465V.
U18 Standby# is low-active: high or open enables output; low makes the oscillator output high-Z. R62=10kΩ correctly pulls Standby# to 1V8. C44=10nF matches the 0.01uF capacitor shown in the datasheet test circuit; this is evidence of adequacy for the characterized circuit, not an explicit minimum-capacitance guarantee. U18 and R59 are DNP by default.
1V8 current budget
Guaranteed exact application totals are unavailable because the datasheets do not specify every device at the exact activity, load and 37.125MHz conditions.

Table

CaseCurrent assessment
Fitted-default, enables lowU15 static table: 2uA typ / 20uA max; U16: 10uA max; U17 exact disabled-current guarantee for PGGK8 is unavailable. Therefore no authoritative total minimum/typical/maximum can be stated.
Fitted-default, U17 clock activeExact 37.125MHz PGGK8 IDD is unavailable. The applicable PGGK table gives 12mA typ / 13mA max at 100MHz, no load, 25°C; use 13.03mA plus output-load current only as a conservative planning reference, not a guaranteed 37.125MHz limit.
Optional U18 fittedExact 37.125MHz current is unavailable. Linear interpolation of the datasheet's 27MHz and 70MHz no-load points gives approximately 6.67mA typ / 7.04mA max; this is an engineering estimate, not guaranteed. U17 CLKIN's typical 5pF adds about 0.334mA and R63 adds about 0.019mA average at 50% duty, giving about 7.02mA typ / 7.39mA estimated max, excluding PCB capacitance.
Both clock buffer and optional oscillator activePlanning reference is about 20.4mA plus the four camera-input capacitive loads. For illustration only, four 5pF loads add about 1.34mA at 37.125MHz and 1.8V.
Trigger switchingU15 static current is small, but dynamic current cannot be guaranteed without trigger activity and camera-input capacitance; its published Cpd point is not characterized at 1.8V. U16 only switches when enable changes; its 1.8V Cpd is 16pF typical.
R64 trigger-OE pull-upAdds approximately 18uA to the 1V8 load only while U16 asserts TRIG_OE_N low; negligible current when the node is high except input leakage. Worst resistor-tolerance current at 1.8V is about 18.2uA.
The project 1V8 rail metadata is 1.5A nominal / 3A maximum, so Block 6 is a small fraction of the rail budget even with the optional oscillator, but camera endpoint capacitance remains required for a final dynamic number.
Connectivity, ERC and endpoint classification
Fresh post-change review found no Block 6 shorts, driver conflicts, floating pins, missing power pins or unconnected wire endpoints. Passive-component and schematic-legibility queries returned no matching findings for R64. The only Block 6 ERC errors remain ten intentional later-block placeholders:
  • Camera endpoints: CAM1_XTRIG…CAM4_XTRIG, CAM1_MCLK…CAM4_MCLK.
  • Input endpoints: HOST_MCLK_IN, EXT_CLK_IN.
These are classified as connector-block omissions, not internal Block 6 faults. TRIG_IN is not a single-pin net because it already connects the four U15 inputs and R54; its external service connector remains a later-block endpoint caveat.
Authoritative post-change net membership:
  • TRIG_OE_N — 6 pins: U16:Y, U15:~1OE, U15:~2OE, U15:~3OE, U15:~4OE, R64:P2.
  • 1V8 — 47 pins: prior 46 members plus R64:P1.
  • Total project nets remain 82; R64 joins existing nets and creates no new net.
Final project counts
  • Components: 135
  • Nets: 82
  • BOM items: 127

  • Corrections made

  • Parts, power and decoupling

  • Trigger path and enable behavior

  • MCLK fan-out and source selection

  • 1V8 current budget

  • Connectivity, ERC and endpoint classification

  • Final project counts