Part Information Review and Datasheet Update


Yes — the incomplete connections are on the PCB layout, not the schematic.
The review shows:
  • Airwires: 7 errors = missing routed traces between pads
  • Floating Pin: clean
  • Single Pin Nets: clean
  • Undriven Nets: clean
That matches Flux’s review definition: an airwire means a net is connected logically but not yet routed as copper on the board
What is already connected in the schematic:
  • GND: J1 pin 2, J3 pin 2, Q1 source, R2 pin 2
  • +24V: J1 pin 1, J2 pin 1, D1 cathode
  • SOL_LOW: J2 pin 2, Q1 drain, D1 anode
  • GPIO_IN: J3 pin 1 to R1
  • GATE: R1, R2, and Q1 gate
So the issue is:
  • the board still needs copper traces between those pads
  • not that J1, J3, or R2 are electrically undefined
Also, when reporting project state, the right approach is to describe what is actually present and separate concerns like unrouted connections from the functional schematic state
What still needs routing

Table


NetPads needing copper connection
GNDJ1, J3, Q1, R2
+24VJ1, J2, D1
SOL_LOWJ2, Q1, D1
GPIO_IN / GATEJ3, R1, R2, Q1
If you want, I can next give you a pad-by-pad manual routing order for J1, J2, J3, D1, Q1, R1, and R2 so you can clear the airwires quickly.
Give routing order
Check all DRC
Show board summary

J1 1 - R1 P1
Q1
Q1 D - U2 2
R2
Resistance
10kΩ
D1
Q1 G - R1 P2
J1 1 - R1 P1
Q1 D - U2 2
Q1 G - R1 P2
U1 1 - U2 1
Q1 D - U2 2
Q1 G - R1 P2
U1 1 - U2 1
U1 1 - U2 1
R1
Resistance
1kΩ
J1
GND
GND
J2
GND
J3
GND
Design Notes
24 V Solenoid Driver
  • Topology: low-side N-channel MOSFET switch
  • Q1: IRLZ44NPBF used as the switching element
  • R1: 1k gate resistor from Jetson GPIO to MOSFET gate
  • R2: 10k pull-down from MOSFET gate to ground so the MOSFET stays off during GPIO reset/high-Z
  • D1: 1N4007 flyback diode placed across the solenoid path
  • U1: 24 V input terminal
  • U2: solenoid output terminal
  • J1: Jetson GPIO input header
Net assignments
  • +24V: U1 pin 1, U2 pin 1, D1 cathode
  • GND: U1 pin 2, J1 pin 2, Q1 source, R2 low side
  • GPIO_IN: J1 pin 1 to R1 input
  • GATE: R1 output to Q1 gate and R2 pull-down top
  • SOL_LOW: Q1 drain, U2 pin 2, D1 anode
Layout intent
  • Keep U1, U2, and J1 on board edges for easy wiring
  • Keep Q1 and D1 close to the high-current solenoid loop
  • Use wider copper for +24V, GND, and SOL_LOW than for GPIO_IN/GATE
  • Use a 2-layer stackup for simplicity and manufacturability
  • Board resized to 80 mm x 70 mm after checking the component bounding box for comfortable fit
Current review status
  • Schematic connectivity is complete for the requested low-side solenoid driver
  • All placed parts have footprints
  • Airwires remain in the layout because detailed trace routing has not been completed yet
  • 24 V Solenoid Driver

  • Net assignments

  • Layout intent

  • Current review status