# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** ameboid - **Created:** 9/24/2024 - **Last Updated:** 9/24/2024 - **Visibility:** Public - **Copies:** 1 ## Key Components ### IC1 — [FUSB302B11MPX](https://www.flux.ai/vasyl/fusb302b11mpx~5c3.md) - Manufacturer Name: onsemi - Manufacturer Part Number: FUSB302B11MPX - Part Type: Integrated Circuit - Datasheet URL: https://www.onsemi.com/pdf/datasheet/fusb302b-d.pdf **Pins:** - CC1 [pin 10] - CC1 [pin 11] - CC2 [pin 14] - CC2 [pin 1] - GND [pin 15] - GND [pin 8] - GND [pin 9] - INT_N [pin 5] - SCL [pin 6] - SDA [pin 7] - VBUS [pin 2] - VCONN [pin 12] - VCONN [pin 13] - VDD [pin 3] - VDD [pin 4] ### U1 — [TLV320AIC3204IRHBT](https://www.flux.ai/adrian95/tlv320aic3204irhbt~2eq.md) - Part Type: Integrated Circuit - Manufacturer Name: Texas Instruments - Manufacturer Part Number: TLV320AIC3204IRHBT - License: https://creativecommons.org/licenses/by/4.0/ - Datasheet URL: https://www.ti.com/lit/ds/symlink/tlv320aic3204.pdf **Pins:** - ~RESET [pin 31] - AVDD [pin 24] - AVSS [pin 17] - BCLK [pin 2] - DIN/MFP1 [pin 4] - DOUT/MFP2 [pin 5] - DVDD [pin 29] - DVSS [pin 28] - EP [pin 33] - GPIO/MFP5_(32) [pin 32] - HPL [pin 25] - HPR [pin 27] - IN1_L [pin 13] - IN1_R [pin 14] - IN2_L [pin 15] - IN2_R [pin 16] - IN3_L [pin 20] - IN3_R [pin 21] - IOVSS [pin 7] - LDO_SELECT [pin 30] - LDOIN [pin 26] - LOL [pin 22] - LOR [pin 23] - MCLK_(1) [pin 1] - MICBIAS [pin 19] - MISO/MFP4 [pin 11] - OVIDD [pin 6] - REF [pin 18] - SCL/SSZ [pin 9] - SCLK/MFP3 [pin 8] - SDA/MOSI [pin 10] - SPI_SELECT [pin 12] - WCLK [pin 3] ### U2 — [TCA6424ARGJR](https://www.flux.ai/adrian95/tca6424argjr~x82.md) - License: https://creativecommons.org/licenses/by/4.0/ - Manufacturer Part Number: TCA6424ARGJR - Manufacturer Name: Texas Instruments Inc. - Part Type: Integrated Circuit - Datasheet URL: https://www.ti.com/lit/ds/symlink/tca6424a.pdf **Pins:** - ~INT [pin 32] - ~RESET [pin 28] - ADDR [pin 26] - EP [pin 33] - GND [pin 25] - P00 [pin 1] - P01 [pin 2] - P02 [pin 3] - P03 [pin 4] - P04 [pin 5] - P05 [pin 6] - P06 [pin 7] - P07 [pin 8] - P10 [pin 9] - P11 [pin 10] - P12 [pin 11] - P13 [pin 12] - P14 [pin 13] - P15 [pin 14] - P16 [pin 15] - P17 [pin 16] - P20 [pin 17] - P21 [pin 18] - P22 [pin 19] - P23 [pin 20] - P24 [pin 21] - P25 [pin 22] - P26 [pin 23] - P27 [pin 24] - SCL [pin 29] - SDA [pin 30] - V_CCI [pin 31] - V_CCP [pin 27] ### U3 — [ESP32-C3-MINI-1-N4](https://www.flux.ai/jecstronic/esp32-c3-mini-1-n4~wbz.md) - Part Type: Module - Datasheet URL: https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf - License: https://creativecommons.org/licenses/by/4.0/ - Manufacturer Name: Espressif Systems - Manufacturer Part Number: ESP32-C3-MINI-1-N4 **Pins:** - 3V3 [pin 3] - EN [pin 8] - GND [pin 51] - GND [pin 36] - GND [pin 49_9] - GND [pin 1] - GND [pin 49_6] - GND [pin 46] - GND [pin 49_3] - GND [pin 43] - GND [pin 49_7] - GND [pin 39] - GND [pin 14] - GND [pin 41] - GND [pin 37] - GND [pin 53] - GND [pin 42] - GND [pin 49_2] - GND [pin 49_1] - GND [pin 45] - GND [pin 11] - GND [pin 38] - GND [pin 52] - GND [pin 2] - GND [pin 48] - GND [pin 49_4] - GND [pin 40] - GND [pin 49_5] - GND [pin 49_8] - GND [pin 44] - GND [pin 47] - GND [pin 50] - IO0 [pin 12] - IO1 [pin 13] - IO10 [pin 16] - IO18 [pin 26] - IO19 [pin 27] - IO2 [pin 5] - IO3 [pin 6] - IO4 [pin 18] - IO5 [pin 19] - IO6 [pin 20] - IO7 [pin 21] - IO8 [pin 22] - IO9 [pin 23] - NC [pin 35] - NC [pin 4] - NC [pin 10] - NC [pin 32] - NC [pin 7] - NC [pin 9] - NC [pin 28] - NC [pin 24] - NC [pin 15] - NC [pin 34] - NC [pin 29] - NC [pin 17] - NC [pin 33] - NC [pin 25] - RXD0 [pin 30] - TXD0 [pin 31] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/ameboid/2-layer-jlcpcb-constraints~oj](https://www.flux.ai/ameboid/2-layer-jlcpcb-constraints~oj).* --- *Generated from [https://www.flux.ai/ameboid/2-layer-jlcpcb-constraints~oj](https://www.flux.ai/ameboid/2-layer-jlcpcb-constraints~oj)*