Hardware Project Start

flux

Architecture is set: 6S pack input, protected 3.3 V buck supply, switched precision divider, 5-minute wake cycle, and 20-second BLE window. I’m now building the schematic and support circuits.

flux

The project is now named 6S Battery Cycle Counter, with the architecture and requirements defined. The schematic build task completed in the background, but I could not retrieve or verify its final report because no ACUs remain.
Open items
  • Inspect the generated schematic and resolve any ERC/connectivity issues.
  • Confirm regulator, divider accuracy, GPIO mapping, and standby current.
  • Create the firmware/BLE service file with deep-sleep and persistent cycle-count logic.
Next step
  1. Restore ACUs.
  2. Ask me to verify and finish the schematic.
  3. After verification, proceed to PCB layout.
Received notification from "6S Battery Counter" that it finished — picking the work back up.

flux

The executor reports completion, but I can’t access or reconcile its detailed output because the account currently has no available ACUs. The project may contain unverified schematic changes; remaining work is to inspect the schematic, run ERC/connectivity checks, confirm the 6S input and low-power design, and document the 5-minute sleep, 20-second BLE, and persistent cycle-count firmware logic after ACUs are restored.
Inspect schematic issues
Review BOM health
Document firmware requirements
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Project Specification
Project Overview
Production-intent, low-cost monitor that measures total voltage of a 6S Li-ion pack and persistently counts qualified charge/discharge cycles. Status: Draft / implementation in progress.
Intended Use
Installed across a protected 6S pack (16.8–25.2 V) as an always-connected, low-power BLE service monitor.
What the Device Should Do
  • Wake every five minutes, enable the pack divider, settle and average samples, update persistent cycle state, advertise BLE for 20 seconds, then deep sleep.
  • Arm only above 24.5 V; increment once when the armed state later falls below 22.0 V; ignore partial events.
  • Retain count and armed state in nonvolatile storage; firmware shall apply threshold hysteresis.
Main Features
  • Total pack-voltage measurement, target ±0.1 V after production calibration.
  • ESP32-C3 module with PCB antenna and native USB Serial/JTAG.
  • Protected high-voltage 3.3 V buck supply.
  • Switched precision divider with defined ADC-off state.
  • BOOT, RESET, low-current status LED, USB-C data, and labeled test points.
System Architecture
Text
6S PACK -> connector -> reverse-polarity protection -> TVS -> HV buck -> 3V3 -> ESP32-C3
                  \-> switched precision divider -> ADC RC filter -> ESP32-C3 ADC
USB-C -> CC resistors + ESD -> native USB GPIOs (VBUS not tied to 3V3)
Hardware Subsystems
  • Input: 2-position terminal block, reverse-polarity MOSFET, surge TVS.
  • Power: documented high-voltage synchronous buck, 3.3 V, >=500 mA.
  • Sensing: GPIO-controlled high-side switch, 0.1% divider, RC-filtered ADC.
  • Compute/radio: ESP32-C3-WROOM-02-N4.
  • USB/debug: USB-C USB 2.0 data only, CC pull-downs, ESD array, native Serial/JTAG.
  • Controls/test: BOOT, RESET, status LED, BAT+, GND, 3V3, ADC and USB/debug test points.
Interfaces and Connections
  • J1: BAT+ / GND, 16.8–25.2 V.
  • J2: USB-C device port; USB data and host detection only; no USB-to-3V3 power path.
  • BLE: onboard PCB antenna.
Power and Runtime Expectations
The board is pack-powered continuously. Deep-sleep current is dominated by ESP32-C3 module sleep current, buck quiescent current, and protection leakage; the voltage divider is disabled in sleep.
Power Tree and Power Budget

Table

Rail/loadSleepActive typicalPeak
ESP32-C3 module~5–15 uA~25–100 mA~350 mA RF transient
Status LED0~0.6 mA~0.6 mA
Enabled divider0~0.23 mA~0.23 mA
3V3 rail design total~5–15 uA~101 mA~351 mA
Buck input at 16.8 V, 85% efficiencyregulator-IQ dominated~23 mA~81 mA
Regulator output capability shall be at least 500 mA. Input connector, reverse protection, and TVS are sized well above the calculated sub-0.1 A operating input current.
Manufacturing and Assembly Expectations
SMD production assembly, 0603/0805 passives where practical, active lifecycle parts, verified footprints, explicit ratings and test points.
Firmware-Relevant Hardware Requirements
  • GPIO9: BOOT strap, 10 kΩ pull-up, button to GND.
  • EN: pull-up, RC delay, reset button to GND.
  • GPIO18/19: native USB D-/D+.
  • Dedicated safe GPIOs for divider enable, ADC input, and LED.
  • ADC calibration at production/bring-up is required to guarantee ±0.1 V pack accuracy.
Physical Design Expectations
Keep the ESP32 antenna edge clear in PCB layout; place buck hot loop compactly; place USB ESD at the connector; place divider/filter away from SW node.
Important Design Decisions
  • Use a module rather than bare RF IC.
  • Use pack power only; USB does not back-power 3V3.
  • Use switched high-side divider topology so no MCU node is exposed to pack voltage while off.
Assumptions
  • The pack includes its own cell-level BMS; this board performs monitoring only.
  • A one-point or two-point production ADC calibration is acceptable for the ±0.1 V target.
  • Ambient and EMC qualification remain product-level responsibilities.
Change Notes
  • Initial requirements captured; component selection and schematic implementation started.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes