PCB Airwire Fix

A

alim8486

The "Airwires" review flagged a error on U1:1V8_LDO, C14:P1.
Reports missing routed traces between pads in a net.
Designators: U1:1V8_LDO, C14:P1; Net: 1V8_FLASH
Context: Reports missing routed traces between pads in a net.
Help me fix this.

flux

I couldn’t modify the PCB because no ACUs are currently available. The remaining fix is to route the 1V8_FLASH airwire between U1:1V8_LDO and C14:P1, then rerun the Airwires/DRC check to confirm the net is fully connected and clearance-safe.
Route 1V8_FLASH trace
Inspect U1 and C14
Check net connectivity
Fix airwire issue
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Files

Schematic

Layout

Preview

Board Bring-Up Plan — USB-C WiFi BLE TH Sensor
Prerequisites
  • Equipment: USB-C current meter or current-limited 5 V supply, DMM, oscilloscope, SWD debugger, 3.3 V USB-UART adapter.
  • Firmware: use the Firmware Starter project file.
  • Safety: do not exceed normal USB-C 5 V input during initial bring-up. The TPS25940 eFuse is configured for ~1 A current limit, ~4.3 V UVLO, ~6.0 V OVP cutoff, and true reverse-current blocking.
1. Visual Inspection
  • Confirm J1 USB-C orientation and shell solder joints.
  • Confirm U1 SiWG917 module orientation and antenna edge/keepout in layout.
  • Confirm U2 TPS259621, U3 MP28301, U4 SHT41, D1-D4, L1, and polarized LED orientation.
  • Inspect for bridges on U1 module castellations/pads and U3 QFN pins.
2. Power Rail Verification

Table

RailSourceExpected VoltageToleranceMeasure AtCurrent LimitPass Criteria
VBUS_RAWJ1 USB-C VBUS4.75–5.25 VUSB sourceJ1 VBUS / U2 INSource limited 100–300 mA first powerPresent only after USB-C attach
VBUS_PROTU2 TPS25940 OUT~VBUS minus small drop<200 mV drop at light loadU2 OUT / C3U2 ~1 A limitNo oscillation, no FLT assertion
3V3U3 MP28301 buck OUT13.3 V±5% initialU3 OUT1 / C5 / U1 VBATT700 mA regulator rating3.135–3.465 V
1V8_FLASHU1 internal 1V8_LDO~1.8 Vper module specU1 1V8_LDO / C14Module internalPresent after U1 powered
Procedure:
  1. With no power, measure resistance from VBUS_RAW, VBUS_PROT, 3V3, and 1V8_FLASH to GND.
  2. Power from a current-limited 5 V source at 100–300 mA for first power-up.
  3. Verify VBUS_RAW, then VBUS_PROT, then 3V3, then 1V8_FLASH.
  4. Check BUCK_SW only with oscilloscope probe ground kept short; expect switching waveform.
  5. Increase current limit only after no shorts/heating are observed.
3. Critical Signal Verification

Table

SignalExpected StateMeasure AtNotes
EFUSE_EN_UVLOHigh when VBUS is validU2 ENR5/R6/R4 divider enables around ~4.3 V rising
EFUSE_OVPBelow trip during normal USB 5 VU2 OVPR5/R6/R4 divider trips around ~6.0 V input
EFUSE_FLT_NHigh when no faultU2 FLT / U1 UULP_VBAT_GPIO_3Open-drain pull-up R7
PWR_PGOODHigh when 3.3 V is validU3 PG1 / U1 UULP_VBAT_GPIO_2Open-drain pull-up R8
POC_INHigh after POC_OUT releaseU1 POC_IN / SW1SW1 pulls low for reset
RESET_NHigh after reset delayU1 RESET_N / J2 pin 10R12/C17 RC
SWO_ISPFloating/high unless SW2 pressedU1 JTAG_TDO_SWOHold SW2 during reset for ISP
4. Connector and Interface Tests

Table

ConnectorTypePins to VerifyTest Method
J1USB-C receptacleVBUS, GND, CC1, CC2, shellContinuity and USB-C attach current check
J210-pin debug header3V3, GND, SWDIO, SWCLK, SWO, RESET_N, UART RX/TXContinuity to U1 and debugger target-detect
5. Programming and Debug Interface
  • SWD: J2 pin 1 3V3, pin 2 SWDIO, pin 4 SWCLK, pins 3/5/9 GND, pin 10 RESET_N.
  • UART ISP: J2 pin 7 UART_RX_MCU, pin 8 UART_TX_MCU; hold SW2 during reset.
Procedure:
  1. Connect SWD debugger and confirm target voltage is 3.3 V.
  2. Attempt target detection and read device ID.
  3. Flash a minimal firmware image that toggles STATUS_LED and prints over debug/UART.
  4. Test SW1 reset and SW2 ISP entry.
6. Functional Validation

Table

TestComponentsExpected ResultPass Criteria
I2C scanU1, U4, R9, R10SHT41 appears at 0x44Address ACKs reliably
T/RH readU4 SHT41Plausible indoor readingsTemp within ambient ±2 °C initially; RH 0–100%
Status LEDU1, R11, LED1LED togglesVisible without excessive current
Wi-FiU12.4 GHz scan/connectNetwork scan succeeds
BLEU1BLE advertising/provisioningAdvertising visible on phone/sniffer
Protection faultU2FLT responds to overloadUse controlled electronic load only
7. Layout-Sensitive Bring-Up Notes
  • Place U1 antenna at board edge and keep antenna clearance free of copper/traces/components on all layers.
  • Place U4 SHT41 away from U3 buck, L1, U1, LED1, and USB-C heat sources; consider thermal slots/air gap.
  • Keep U3/L1 switching loop compact and away from antenna and sensor.
Pass/Fail Summary

Table

SectionResultNotes
Visual Inspection[ ] Pass / [ ] Fail
Power Rails[ ] Pass / [ ] Fail
Critical Signals[ ] Pass / [ ] Fail
Connectors[ ] Pass / [ ] Fail
Programming[ ] Pass / [ ] Fail
Functional Validation[ ] Pass / [ ] Fail
Board Status: [ ] Ready for deployment / [ ] Requires rework

  • Prerequisites

  • 1. Visual Inspection

  • 2. Power Rail Verification

  • 3. Critical Signal Verification

  • 4. Connector and Interface Tests

  • 5. Programming and Debug Interface

  • 6. Functional Validation

  • 7. Layout-Sensitive Bring-Up Notes

  • Pass/Fail Summary