I’ll execute Stage 2 directly from your attached instructions, without creating another planning document or changing PCB layout. I’ll preserve Stage 1 and verify the MCU connections and 23 NC pins.
Stage 2 electrical capture is complete: all 21 components are added and wired, U1 has 41 connected pins and 23 NC pins, and the Stage 1 interfaces plus future peripheral net labels are connected as specified; Y1 is a verified 8 MHz crystal.
Compact center placement and drawn-wire cleanup remain blocked by unavailable schematic-arrangement tools; ERC retains the existing VSYS-undriven finding and intentional future-interface stubs. No PCB layout or routing was changed, and no pre-planning document was created.
I haven’t performed any additional edits or verification this turn. The completion notice alone does not establish whether Stage 2 was captured correctly; I still need to inspect the project and check the 21 components, all MCU connections, the 23 NC pins, and the interface labels against the approved net table.
The project currently lists 38 components and 40 nets, consistent with the expected component count after Stage 2, but I have not verified its wiring or NC flags. No additional changes were made this turn.
Remaining work is to check the 21 Stage 2 components against the approved net table, verify all 23 MCU NC pins, and confirm the Stage 1 connections and later-stage interface labels. Execution stopped because your ACUs ran out.
Capture the Power & USB block at the left of the schematic, following the approved PDF designators, values and exact source connectivity. This is a plan only: no schematic mutations are performed. Critical PDF extraction is OCR-derived; verify library pin mapping and manufacturer requirements before wiring. Do not silently substitute parts, change topology, rename source nets, or implement corrections. Document discrepancies for approval.
Stage 1 parts: J1, J2, U6, Q1, D1, U5; R1–R5; C1–C4 and C18. Include JP1 as the source-defined VSYS-to-ARM_BUS pass-through for the later output block. Later-stage parts remain absent until their capture stage. Preserve VBAT_SENSE for U1.8 (PC0) in the MCU stage.
1. Verify symbols and footprints
Resolve exact parts before placement:
J1 TYPE-C-31-M-12; source logical contacts and physical footprint mapping must agree, including internally combined or duplicated contacts.
J2 keyed JST-PH 2-pin battery connector; choose exact orientation/variant and verify mating polarity before footprint approval.
U6 USBLC6-2SC6, SOT-23-6.
Q1 AO3401A, SOT-23: source pin 1=G, 2=S, 3=D.
D1 SS14, SMA: source D1.1=VBUS/anode, D1.2=VSYS/cathode. Verify library terminal identity rather than assuming diode numbering.
If an exact verified part is unavailable, report the specific blocker and continue independent supported parts. Do not alter source pin semantics to accommodate a wrong library symbol.
2. Perform pre-capture power review
Enumerate planned MCU, sensors, LEDs, buzzer and external 3V3 header loads; distinguish normal and peak current. Review USB VBUS through D1 into U5 and full 1S LiPo voltage range through Q1. Evaluate regulator dropout and USB-mode thermal dissipation, plus source-switch behavior and possible backfeed. ARM_BUS load current bypasses U5 but still loads D1/Q1, battery connector and source paths.
Source fidelity is required; this review must record unverified load allowances, not invent external loads or change the selected power path. No charger, fuse or extra protection parts are authorized in this stage. Missing output load requirements block load-rating approval, not independent schematic capture of the specified power/USB block. Capture is not approval for flight or hazardous-load use.
3. Place and configure the left-hand functional block
Arrange J1/U6 as the USB interface, J2/Q1/D1 as source selection, U5/C1–C4 as regulation, and R4/R5/C18 as monitoring. Keep USB data paths directed toward the future central MCU and 3V3/VSYS/ARM_BUS interfaces clearly named. Use the source designators and values; no unnamed replacement rails.
Table
Parts
Value / purpose
R1, R2
5.1k USB-C CC pull-downs
R3
100k Q1 gate/VBUS pull-down
R4, R5
100k / 100k VSYS monitor divider
C1
10uF VSYS bulk
C2
1uF VSYS bypass
C3
10uF 3V3 bulk
C4
100nF 3V3 bypass
C18
100nF monitor filter
Passive voltage ratings and tolerances must suit source voltages and capacitance derating; the PDF does not specify exact rated variants. Record selected ratings without changing nominal source values.
4. Wire exact Stage 1 connectivity
The following table is the source-netlist subset, not a new topology. Preserve terminal 1/2 assignment for generic passives.
Mark J1.A8/J1.B8 (SBU1/SBU2) and U5.4 as no-connect. Where a verified connector library combines physical contacts, preserve electrical equivalence and record the source-to-library mapping explicitly.
Q1 gate is VBUS, source VSYS, drain VBAT. D1 anode is VBUS and cathode VSYS. U5 EN is tied to VSYS. Do not connect VBAT directly to VBUS or 3V3. Do not connect VSYS directly to 3V3.
VBAT_SENSE -> future U1.8 / PC0, unchanged. It is VSYS/2, not raw VBAT/2.
3V3/GND -> MCU, sensors, headers and buzzer in later stages.
ARM_BUS -> future J6.1 and J7.1; do not add those connectors yet.
Use named net interfaces without dummy components. ARM_BUS has only JP1.2 at this stage; USB data and monitor nets intentionally await MCU termination.
6. Bounded verification and completion gates
Check exact Stage 1 inventory: 17 parts (six named primary parts, JP1, five resistors, five capacitors), preserving source designators. Stage 1 subset has 11 named nets.
Compare every table connection and NC against the schematic, not merely matching net names.
Confirm USB polarity and orientation duplication, independent CC pull-downs, grounded shield, U6 rail connection, diode polarity, Q1 G/S/D/body-diode direction and U5 pins.
Confirm monitor divider remains R4 to VSYS, R5 to GND and C18 to GND; note future PC0 endpoint.
Run ERC and visual wire review. Resolve concrete wiring errors; distinguish expected incomplete-stage endpoints from actual faults. Do not claim full-board ERC completion.
Record unverified headroom, thermal/load limits, battery protection, USB VBUS sensing and symbol/footprint discrepancies as open items. Do not label the design electrically validated while these remain unresolved.
Deliver the captured block plus connectivity/part-mapping results and explicit blockers. Proceed to the approved MCU stage only after Stage 1 checks are complete; PCB sizing, placement and routing are outside this plan.
Deliverable
A source-faithful Power & USB schematic block on the left, with named pass-through nets ready for later capture, verified Stage 1 connectivity, and a documented list of unresolved electrical or library constraints. Source switching does not charge the battery; USB may energize ARM_BUS when JP1 is fitted.
Scope and fidelity
1. Verify symbols and footprints
2. Perform pre-capture power review
3. Place and configure the left-hand functional block