Project Idea Start

flux

I’ll execute Stage 2 directly from your attached instructions, without creating another planning document or changing PCB layout. I’ll preserve Stage 1 and verify the MCU connections and 23 NC pins.

flux

Stage 2 electrical capture is complete: all 21 components are added and wired, U1 has 41 connected pins and 23 NC pins, and the Stage 1 interfaces plus future peripheral net labels are connected as specified; Y1 is a verified 8 MHz crystal.
Compact center placement and drawn-wire cleanup remain blocked by unavailable schematic-arrangement tools; ERC retains the existing VSYS-undriven finding and intentional future-interface stubs. No PCB layout or routing was changed, and no pre-planning document was created.
"Stage 2 MCU Setup" completed.

flux

I haven’t performed any additional edits or verification this turn. The completion notice alone does not establish whether Stage 2 was captured correctly; I still need to inspect the project and check the 21 components, all MCU connections, the 23 NC pins, and the interface labels against the approved net table.
Execution stopped because your ACUs ran out.
"Stage 2 MCU Setup" completed.

flux

The project currently lists 38 components and 40 nets, consistent with the expected component count after Stage 2, but I have not verified its wiring or NC flags. No additional changes were made this turn.
Remaining work is to check the 21 Stage 2 components against the approved net table, verify all 23 MCU NC pins, and confirm the Stage 1 connections and later-stage interface labels. Execution stopped because your ACUs ran out.
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Files

Schematic

Layout

3D View

Schematic Module Plan
Scope and evidence
Parsed Flight_Computer_Schematic.pdf, sections 1–7 (power/USB, MCU, sensors, outputs, headers, netlist, BOM). Extraction is OCR-based; critical pin numbers, polarities and values require visual/datasheet verification before capture. This document is a module plan, not an electrically validated schematic. Source reports 71 parts, 49 nets and zero internal netlist check failures; those checks do not establish electrical correctness. No components or wiring have been created.
Proposed schematic modules

Table

ModuleSource partsResponsibility and interfaces
USB-C interface and ESDJ1, U6, R1–R2USB input VBUS/GND, separate CC1/CC2 5.1k pull-downs; USB_DP/USB_DM to MCU through ESD protection. Join both connector orientations. Ground shield as source specifies; SBU unused.
Source selection and regulationJ2, Q1, D1, U5, R3, C1–C4USB VBUS via SS14 to VSYS; LiPo VBAT via AO3401A to VSYS; Q1 gate on VBUS with 100k pull-down. AP2112K input and EN on VSYS, output 3V3. C1/C3 10uF, C2 1uF, C4 100nF.
Supply monitorR4–R5, C18Two 100k resistors divide VSYS to VBAT_SENSE; 100nF ADC filter to GND; MCU PC0. Despite its name this measures VSYS, not raw battery voltage when USB is connected.
MCU core and boot/resetU1, SW1–SW2, R6–R7, C5–C15All MCU power pins, VBAT tied to 3V3, analog supply, four VDD bypass caps, bulk and analog bypass; separate VCAP1/VCAP2 2.2uF caps to ground. Reset button and 100nF; BOOT0 switch to 3V3 and 10k pull-down; BOOT1 10k pull-down. Do not connect VCAP nets to 3V3.
HSE clockY1, C16–C178MHz crystal between PH0/PH1, grounded case pads, two 12pF C0G capacitors. Source specifies CL=10pF and assumes about 4pF stray; values remain subject to crystal/layout validation.
IMUU2, R18, C19–C21ICM-42688-P on shared SPI1, independent ICM_CS with 10k pull-up, two interrupts; source includes 100nF, 2.2uF, 10nF support caps. Associate capacitors with exact supply pins after datasheet review.
BarometerU3, R19, C22–C23BMP581 on SPI1, BMP_CS 10k pull-up, BMP_INT; two 100nF caps.
MagnetometerU4, R20, C24–C26MMC5983MA on SPI1, MMC_CS 10k pull-up, MMC_INT; 1uF and 100nF supply caps, 10uF MMC_CAP to ground. Verify reserved pins and CAP requirements from datasheet.
Armed output supply and driversJP1, J6–J7, Q3–Q4, R10–R13JP1 connects VSYS to ARM_BUS. Each connector exposes ARM_BUS and switched low-side drain; AO3400A sources grounded, 100-ohm series gate resistors and 100k gate pull-downs.
Buzzer and statusJ8, Q2, R8–R9, D2–D3, R14–R153V3 active buzzer low-side switch; 100-ohm gate series and 100k pull-down. Green/red LEDs from PC6/PC7 through 1k to LED anodes; cathodes grounded.
Debug and expansionJ3–J5, R16–R17SWD 1x6, USART1 1x4, I2C1 1x4; separate 4.7k I2C pull-ups to 3V3.
MCU signal allocation from source

Table

InterfaceMCU port / physical pinNet
HSEPH0 / 5; PH1 / 6HSE_IN; HSE_OUT
ADCPC0 / 8VBAT_SENSE
SPI1PA5 / 21; PA6 / 22; PA7 / 23SPI1_SCK; SPI1_MISO; SPI1_MOSI
Sensor CSPA4 / 20; PC4 / 24; PC5 / 25ICM_CS; BMP_CS; MMC_CS
Sensor interruptsPB0 / 26; PB1 / 27; PC2 / 10; PC3 / 11ICM_INT1; ICM_INT2; BMP_INT; MMC_INT
USB FSPA11 / 44; PA12 / 45USB_DM; USB_DP
DebugPA13 / 46; PA14 / 49; PB3 / 55; NRST / 7SWDIO; SWCLK; SWO; NRST
USART1PA9 / 42; PA10 / 43UART_TX; UART_RX
I2C1PB8 / 61; PB9 / 62I2C1_SCL; I2C1_SDA
OutputsPA8 / 41; PB6 / 58; PB7 / 59BUZ_CTRL; OUT1_CTRL; OUT2_CTRL
LEDsPC6 / 37; PC7 / 38LED1_CTRL; LED2_CTRL
BootBOOT0 / 60; PB2 / 28BOOT0; BOOT1
Shared SPI source setting: mode 0, at most 10MHz. Treat this as a source proposal; confirm each sensor's supported mode/rate and MISO tri-state behavior before firmware use.
Header pin order from source
  • J3 SWD: 1=3V3, 2=SWDIO, 3=SWCLK, 4=NRST, 5=SWO, 6=GND.
  • J4 UART: 1=3V3, 2=UART_TX (MCU out), 3=UART_RX (MCU in), 4=GND.
  • J5 I2C: 1=3V3, 2=I2C1_SCL, 3=I2C1_SDA, 4=GND.
  • J2 battery: 1=VBAT, 2=GND; verify actual mating cable polarity.
  • J6/J7 outputs: 1=ARM_BUS, 2=OUT1_N/OUT2_N.
  • J8 buzzer: 1=3V3, 2=BUZ_N.
Findings and decisions pending before schematic capture
  1. No battery charger or battery protection is shown. USB power selection does not charge the LiPo. Define external charging and protected battery requirements explicitly.
  2. VBAT_SENSE is VSYS/2. Preserve source connectivity unless intentionally changing it; label its meaning clearly in firmware and schematic notes.
  3. LDO headroom and thermal budget are unverified. Check full LiPo voltage range, dropout near depletion, USB-mode dissipation and header/buzzer loads before approving AP2112K operating limits.
  4. Output load specifications are absent. Establish load type, continuous/peak current and voltage before sizing fuses, clamps/flyback protection, connectors and copper. Treat OUT1/OUT2 as unspecified generic load switches, not approved deployment/pyrotechnic channels.
  5. JP1 disconnects only output positive supply. USB can energize ARM_BUS through VSYS when JP1 is fitted. Gate pull-downs are not a complete safety architecture; keep hazardous loads disconnected during bring-up. Source BOM instruction 'remove before flight' needs clarification against intended output use.
  6. USB VBUS sensing is not allocated to an MCU pin in the source. PA9 is USART1_TX. Verify STM32 USB device/DFU VBUS-sensing requirements and firmware configuration rather than silently repurposing UART_TX.
  7. OCR text mixes pin-name and net-label order. Use source netlist to resolve ordering, then confirm actual library pins against manufacturer datasheets, especially J1/U6, MOSFET polarity and sensor reserved pins.
  8. Connector part versus depicted terminals needs verification. Confirm TYPE-C-31-M-12 symbol/footprint mapping accommodates the source's duplicated USB/VBUS/GND contacts; do not assume OCR contact labels match library terminal numbering.
  9. Source gives crystal ESR limit 150 ohms and capacitor assumptions; confirm selected crystal variant and oscillator suitability rather than treating these as validated manufacturer facts.
Capture order and acceptance checks
  1. Verify library symbols/footprints and source pin mappings; preserve designators and named nets.
  2. Capture USB/source-selection/regulator and supply monitor; complete load/thermal review.
  3. Capture MCU supplies, VCAP, clock and boot/reset.
  4. Capture each sensor as a separate block, sharing only SPI bus, power and ground; retain independent CS and interrupt nets.
  5. Capture debug/expansion, LEDs and buzzer; capture OUT1/OUT2 after load constraints are established.
  6. Cross-check every source net and NC pin against the PDF netlist; reconcile source count of 49 nets/71 parts, inspect ERC, and explicitly review USB polarity, MOSFET body-diode direction, reserved pins and power domains.
Suggested schematic arrangement: power/USB on left, MCU central with clock/reset nearby, three sensors grouped on right, debug/expansion below MCU, and outputs separate at lower right. Placement is a proposed organization, not a PCB layout.

  • Scope and evidence

  • Proposed schematic modules

  • MCU signal allocation from source

  • Header pin order from source

  • Findings and decisions pending before schematic capture

  • Capture order and acceptance checks