# [2-layer] JLCPCB Constraints ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** ak1 - **Created:** 10/15/2024 - **Last Updated:** 10/15/2024 - **Visibility:** Public ## Key Components ### Q1 — [IRFP260NPBF](https://www.flux.ai/adrian95/irfp260npbf~6kh.md) - Datasheet URL: https://www.infineon.com/dgdl/irfp260npbf.pdf - Manufacturer Part Number: IRFP260NPBF - Part Type: Transistor - Manufacturer Name: Infineon Technologies - License: https://creativecommons.org/licenses/by/4.0/ **Pins:** - D [pin 3] - G [pin 1] - S [pin 2] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/ak1/2-layer-jlcpcb-constraints~tc](https://www.flux.ai/ak1/2-layer-jlcpcb-constraints~tc).* --- *Generated from [https://www.flux.ai/ak1/2-layer-jlcpcb-constraints~tc](https://www.flux.ai/ak1/2-layer-jlcpcb-constraints~tc)*