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Corrected ESP32-S3 Pin Map — Master Industrial Gateway
Updated: 2026-06-25 for simplified / downgraded design.
Design Rules Applied
  • Reserved GPIO43/GPIO44 for CP2102 UART0 programming/debug.
  • Avoided GPIO35, GPIO36, and GPIO37 due to ESP32-S3-WROOM-1-N16R2 PSRAM risk.
  • Avoided GPIO45 and GPIO46 because they are boot strapping pins.
  • Removed BG95-M3 cellular, OLED connector, RS232 console, SC16IS752 #3, RS485 ports 4, 6, and 7, and digital inputs DI1/DI2.
  • Used one shared SPI bus to fit the available safe GPIO count.
  • Removed dedicated microSD card-detect GPIO; firmware should detect card presence by mount/probe unless a GPIO is freed later.
Updated Pin Map

Table

FunctionESP32-S3 GPIONotes
BOOT buttonGPIO0Bootloader entry only
I2C SDAGPIO1DS3231 RTC only
I2C SCLGPIO2DS3231 RTC only
W5500 RSTGPIO8Ethernet reset
W5500 INTGPIO9Ethernet interrupt
W5500 CSGPIO10Ethernet chip select
SPI MOSIGPIO11Shared SPI bus
SPI SCKGPIO12Shared SPI bus
SPI MISOGPIO13Shared SPI bus
LoRa CSGPIO15Ra-02 chip select
LoRa IRQGPIO16Ra-02 interrupt
LoRa RSTGPIO17Ra-02 reset
RS485 Port 1 TXGPIO18Native ESP32 UART
RS485 Port 1 RXGPIO21Native ESP32 UART
SC16IS752 #1 CSGPIO33SPI chip select
microSD CSGPIO38No card-detect GPIO
SC16IS752 #2 CSGPIO39SPI chip select
SC16IS752 #1 IRQGPIO40Interrupt
SC16IS752 #2 IRQGPIO41Interrupt
UART0 TXD to CP2102GPIO43Reserved programming/debug
UART0 RXD from CP2102GPIO44Reserved programming/debug
RS485 Port 1 DEGPIO47Direction enable
Spare GPIOs
  • GPIO4, GPIO5, GPIO6, GPIO7: freed by removing BG95-M3 cellular.
  • GPIO14, GPIO48: freed by removing MAX3232 RS232 console.
  • GPIO34, GPIO42: freed by removing SC16IS752 #3.
  • GPIO19, GPIO20: freed by removing digital inputs; these are ESP32-S3 native USB pins and remain unused for now.
Pins Intentionally Not Used
  • GPIO3: avoided to keep strapping/JTAG behavior simple.
  • GPIO35, GPIO36, GPIO37: avoided due to PSRAM risk on N16R2.
  • GPIO45, GPIO46: avoided because they are boot strapping pins.
Shared SPI Bus
  • SCK: GPIO12
  • MOSI: GPIO11
  • MISO: GPIO13
  • Devices: W5500, Ra-02, microSD, SC16IS752 #1, SC16IS752 #2
Remaining Caveats
  • GPIO19/GPIO20 are native USB pins and are intentionally unused in the simplified design because CP2102 UART programming is selected.
  • Current schematic note: the retained SC16IS752 #2 chip-select was moved from GPIO19 to GPIO42 because this ESP32 symbol does not expose GPIO33.
  • RS485 port 4 is removed. The associated SC16IS752 channel pins on IC7 are intentionally unused/no-connect.
  • If hardware microSD card-detect is mandatory, a spare GPIO can now be assigned from the freed GPIO list.
  • This pin map updates the project documentation; schematic net changes/removal must be applied separately if not already done.

  • Design Rules Applied

  • Updated Pin Map

  • Spare GPIOs

  • Pins Intentionally Not Used

  • Shared SPI Bus

  • Remaining Caveats