The display subsystem uses Good Display GDEM0154D67WT as DS1, with active Amphenol F34G-1A7Q1-E8C24 as board connector J1. The previous GDEW0102T4 / 30-pin subsystem is retired from the active design. The watch outline remains 40 × 36 mm; the panel is oriented as 37.32 mm W × 31.80 mm H.

The panel is 200 × 200 pixels with a 27.00 × 27.00 mm active area and 31.80 × 37.32 × 1.00 mm outline. Its interface is a 24-pin, 0.5 mm-pitch FPC. The selected connector is a 24-position, 0.5 mm, right-angle, bottom-contact receptacle; the folded front-contact panel tail faces downward at the PCB connector in the intended watch stack.

The datasheet defines the pin functions, VDDIO-to-VCI connection, and open-pin requirements. BS1 low selects 4-wire 8-bit SPI, and BUSY is asserted high while the panel is busy. VCI is specified for 2.2–3.7 V operation; the watch uses 3.3 V.

The page-25 reference drawing was copied into the schematic with drawing-only nominal values read directly from the circuit artwork:

The parts table calls for a 47 µH NR3015-class inductor, Si1308EDL-class MOSFET, MBR0530-class diodes, 1% 0603/0805 resistors rated at least 0.05 W, and X5R/X7R 0603/0805 capacitors rated at least 25 V. L5 uses a slightly larger compact equivalent because the named 47 µH NR3015 part has materially lower current capability; NRS4018T470MDGJ provides 0.60 A minimum saturation current in a 4 mm, 1.8 mm-high package. The table independently verifies the Q1 and diode electrical classes.

Implemented booster nets:

Firmware must use an SSD1681-compatible 200 × 200 driver, active-high BUSY handling, 4-wire SPI initialization, correct panel waveform/LUT handling, and revised framebuffer/update timing. The operating range is −25 °C to +50 °C and storage range is −25 °C to +70 °C.

Pin-by-pin net inspection confirms DS1 and J1 share the preserved MCU nets and the complete booster topology. DS1/J1 pins 6 and 7 are now tied to GND as required by the exact panel specification; DS1 pins 1, 4, and 19 remain intentionally open, and BS1 is grounded for 4-wire SPI. All implemented reference capacitors are ceramic X7R 25 V parts in explicit 0603/0805 packages; the positive/negative internal rails are approximately +20 V/−20 V, so 25 V is the minimum specified rating and should not be reduced. DRC reports no display-part body or copper overlaps after shifting L5 0.15 mm left. ERC has one justified reusable-part typing false positive: the panel datasheet requires DS1 pin 19 VPP to remain open, but the library terminal is typed as a power input, so Power input not connected: DS1:VPP remains and must not be cleared by wiring VPP to a rail. No other display-block ERC finding remains. Remaining release checks are physical: confirm panel-tail contact face, pin-1 orientation, stiffener/fold direction, insertion depth, latch access, service bend radius, and strain relief on production samples before freezing enclosure and connector placement. PCB routing was intentionally not performed.