Project Cover Page


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Screenshot 2026-07-10 at 11.04.28 a.m. Background Removed

The PCB render is now set as the 10x10 LED Matrix project cover image and verified successfully.
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Can you make the PC be a different color? Do I have to do that manually?
Can you make the board a different color?

Project Specification
Project Overview
  • Status: Draft
  • Device: 10×10 monochrome red LED matrix module.
  • Purpose: Display externally generated patterns using multiplexed row drive and constant-current column sinks.
Intended Use
  • Prototype/display module controlled by an external MCU.
  • 5 V powered; logic inputs compatible with 3.3 V or 5 V controllers.
What the Device Should Do
  • Independently control 100 red LEDs arranged as 10 rows × 10 columns.
  • Refresh one row at a time using a 4-bit row address and row-enable signal.
  • Load column data through a cascaded serial LED-driver chain.
  • Default to a blank display when the controller is absent or starting.
Main Features
  • 100 monochrome red SMD LEDs.
  • 10 mm LED pitch target for PCB layout.
  • Two cascaded 16-channel constant-current sink drivers.
  • Ten P-channel MOSFET high-side row switches.
  • 4-to-16 HCT decoder for row selection.
  • 3.3 V/5 V-compatible external control interface.
  • 5 V terminal-block input with resettable fuse and bulk decoupling.
System Architecture

Diagram


5 V input PTC and filtering PMOS row switches HCT logic and LED drivers External MCU HCT SPI buffers 4-to-16 row decoder Two cascaded constant-current drivers 10x10 LED matrix
Hardware Subsystems
  • Power: 5 V input, 500 mA resettable PTC, local bulk and ceramic decoupling.
  • Column drive: Two STP16CP05 constant-current sink drivers at approximately 20 mA peak per active LED.
  • Row drive: Ten P-channel MOSFETs selected by a 74HCT154 decoder.
  • Logic interface: Buffered DATA, CLK, LATCH, and OE/BLANK plus row address and enable signals, with 4.7 kΩ input series protection.
  • Display: 100 red LEDs, logically grouped into ten rows and ten columns.
Interfaces and Connections
  • Power connector: +5 V and GND.
  • Controller header: GND, DATA, CLK, LATCH, OE/BLANK, ROW_A0–ROW_A3, ROW_EN, 3.3 V-safe serial data output, and spare pins.
Power and Runtime Expectations
  • External regulated 5 V source.
  • One selected row at a time.
  • Up to ten LEDs active in the selected row.
Power Tree and Power Budget

Table


LoadEstimated peak
Active LED row: 10 × 20 mA200 mA
Two LED drivers and logic25 mA
Switching/allowance25 mA
Estimated board peak250 mA
  • Input protection is sized at 500 mA hold current to provide startup and tolerance margin.
  • Each LED has about 2 mA average current at 1:10 multiplexing when programmed for 20 mA peak.
Manufacturing and Assembly Expectations
  • SMD logic, drivers, MOSFETs, passives, and LEDs.
  • Through-hole power terminal and controller header.
  • PCB layout to maintain 10 mm center-to-center LED spacing.
Firmware-Relevant Hardware Requirements
  • Shift 32 serial bits per display update; only ten assigned column bits are used.
  • Blank outputs while changing row address and column data to avoid ghosting.
  • Valid row addresses are 0–9; addresses 10–15 must remain blanked.
Physical Design Expectations
  • LED centers on a 10 mm square grid.
  • Approximate illuminated area: 90 mm × 90 mm between outer LED centers.
  • Final board outline will be selected during PCB layout; a custom outline is preferred.
Important Design Decisions
  • Red LEDs are assumed because monochrome color was unspecified.
  • Two cascaded drivers are retained per the confirmed default, despite unused output capacity.
  • HCT logic is used so 3.3 V MCU signals are valid while the board operates from 5 V.
Assumptions
  • External controller provides 3.3 V or 5 V push-pull logic and holds its outputs low or high-impedance when the matrix board is unpowered.
  • BLANK and ROW_ENABLE_N default inactive using local +5 V pull-ups.
  • Firmware provides 2–5 µs blanking/dead time around row changes.
  • Refresh timing and PWM brightness are implemented in firmware.
  • 20 mA is a peak multiplex current, not continuous average current.
Change Notes
  • Initial schematic architecture established from the confirmed defaults.
  • Added 4.7 kΩ protected controller inputs, 470 Ω PMOS gate resistors, local +5 V fail-safe pull-ups, and a 3.3 V-safe SDO divider after electrical review.
  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes