Project Cover Page

adriangispert

Can you help me make this the cover page of the project?

Screenshot 2026-07-10 at 11.04.28 a.m. Background Removed.png

Worked for 2 mins 15 sec

flux

The PCB render is now set as the 10x10 LED Matrix project cover image and verified successfully.

Review, optimize, export

Run design review

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Check power integrity

Prepare manufacturing files

adriangispert

Can you make the PC be a different color? Do I have to do that manually?

adriangispert

Can you make the board a different color?

Files

Schematic

Layout

3D View

D42

D59

D71

D79

D85

D78

D89

D20

D72

D97

D45

D93

D22

D60

D69

D91

D47

D53

D16

D32

D92

D41

D18

D50

D77

D100

D48

D40

D44

D99

D10

D66

D82

D95

D56

D68

D26

D98

D49

D54

D36

D29

D34

D33

D51

D43

D28

D24

D14

D73

D57

D17

D30

D67

D74

D94

D62

D13

D58

D90

D37

D52

D35

D19

D96

D88

D11

D83

D25

D23

D80

D27

D15

D38

D76

D64

D31

D61

D46

D63

D39

D81

D65

D55

D86

D87

D84

D70

D75

D12

D21

R38

Resistance

470Ω

R28

Resistance

4.7kΩ

R40

Resistance

470Ω

R37

Resistance

470Ω

R20

Resistance

100kΩ

R18

Resistance

100kΩ

R11

Resistance

100kΩ

Resistance

1.00kΩ

Resistance

100kΩ

Resistance

100kΩ

R25

Resistance

4.7kΩ

Resistance

100kΩ

R36

Resistance

470Ω

Resistance

1.00kΩ

R27

Resistance

4.7kΩ

R23

Resistance

6.8kΩ

R39

Resistance

470Ω

Resistance

100kΩ

Resistance

100kΩ

R17

Resistance

100kΩ

R30

Resistance

4.7kΩ

R19

Resistance

100kΩ

R13

Resistance

100kΩ

R10

Resistance

100kΩ

Resistance

100kΩ

Resistance

100kΩ

R29

Resistance

4.7kΩ

R42

Resistance

470Ω

R34

Resistance

470Ω

R31

Resistance

4.7kΩ

R41

Resistance

470Ω

R12

Resistance

100kΩ

R21

Resistance

100kΩ

R26

Resistance

4.7kΩ

R24

Resistance

4.7kΩ

R16

Resistance

100kΩ

R32

Resistance

4.7kΩ

R35

Resistance

470Ω

R33

Resistance

470Ω

R14

Resistance

100kΩ

R15

Resistance

100kΩ

R22

Resistance

3.3kΩ

Capacitance

47uF

Capacitance

100nF

Capacitance

100nF

Capacitance

100nF

Capacitance

10uF

Capacitance

100nF

Q10

Board Bring-Up Plan — 10x10 LED Matrix

Prerequisites

Bench supply set to 5.0 V with adjustable current limit.
Multimeter, oscilloscope, and external 3.3 V or 5 V MCU/controller.
Safety: observe LED and IC orientation; begin with a 100 mA supply limit and no controller attached.

1. Visual Inspection

Check U1/U2 exposed pads for solid ground soldering and bridges.
Verify D1–D100 polarity is consistent.
Verify Q1–Q10 orientation and J1/J2 pin-1 markings.
Confirm R1/R2 are 1.00 kΩ, R33–R42 are 470 Ω, and F1 is populated.

2. Power Rail Verification

Table

Rail	Source	Expected	Measure At	Initial Limit	Pass Criteria
+5V_RAW	J2 pin 1	5.0 V	F1 P1	100 mA	4.75–5.25 V
+5V	F1 P2	near 5.0 V	C5 P1	100 mA	within 0.15 V of +5V_RAW at idle
GND	J2 pin 2	0 V	C5 P2	—	continuity below 1 Ω

Unpowered: verify resistance from +5V to GND is not a hard short.
Apply 5.0 V at 100 mA limit with J1 disconnected.
Confirm BLANK_IN and ROW_ENABLE_N are HIGH and all LEDs remain off.
Idle current should remain below 50 mA. Investigate any lit LED or current limiting.

3. Critical Signal Verification

Table

Signal	Expected Idle State	Probe Location
BLANK_IN	HIGH	U4 4A
BLANK_5V	HIGH	U1/U2 OE
ROW_ENABLE_N	HIGH	U3 E1
ROW_GATE_0–9	HIGH	U3 Y0–Y9
PMOS_GATE_0–9	HIGH	Q1–Q10 gates

4. Connector Tests

Table

Connector	Pins	Test
J2	1 = +5V_RAW, 2 = GND	polarity and continuity
J1	2/4 = GND; 3 DATA; 5 CLK; 6 LATCH; 7 BLANK; 8–11 ROW_A0–A3; 12 ROW_ENABLE_N; 13 SDO_3V3	continuity to series resistors and destination logic

5. Controller Test Sequence

Power the matrix board before enabling controller outputs, or keep controller pins low/high-impedance while +5 V is absent.
Hold BLANK HIGH and ROW_ENABLE_N HIGH.
Shift 32 zero bits and pulse LATCH.
Select row address 0, drive ROW_ENABLE_N LOW, wait 2–5 µs, then drive BLANK LOW.
Repeat for addresses 0–9; never enable addresses 10–15 for display operation.

6. Functional Validation

Table

Test	Input	Expected Result	Pass Criteria
Single pixel	one column bit, row 0	D1 only	no adjacent-row/column glow
Row walk	all columns on, rows 0–9	one complete row at a time	no overlap or ghosting
Column walk	each column individually	one vertical column	correct mapping COL0–COL9
Full pattern	all ten columns for every row	all pixels visually uniform	supply current approximately 200–250 mA
SDO level	logic HIGH shifted through chain	J1 pin 13	3.0–3.6 V

7. Oscilloscope Checks

Confirm BLANK is HIGH during every row-address transition.
Confirm both old and new PMOS gates are not low simultaneously outside the permitted switching transient.
Start with 2–5 µs row dead time and reduce only if waveforms show clean turn-off and no ghosting.
Check +5 V droop at C6 during an all-columns-on row; target less than 250 mV peak-to-peak.

Pass/Fail Summary

Table

Section	Result	Notes
Visual inspection	[ ] Pass / [ ] Fail
Power rails	[ ] Pass / [ ] Fail
Idle safety states	[ ] Pass / [ ] Fail
Connector mapping	[ ] Pass / [ ] Fail
Pixel/row/column tests	[ ] Pass / [ ] Fail
Current and ripple	[ ] Pass / [ ] Fail

Board Status: [ ] Ready for layout/manufacturing validation / [ ] Requires rework

Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Connector Tests
5. Controller Test Sequence
6. Functional Validation
7. Oscilloscope Checks
Pass/Fail Summary