Part Metadata Audit and Update

flux

Done. I assigned every one of the 72 pins to exactly one primary function group and updated the terminal metadata with Pin Group and Pin Type.
I also saved the full exclusive grouping table in the project file STM32U3C5JIY6QTR Pin Groups. Spot-checks passed, and review shows no open errors or warnings.
A

adrian95

The pins are already grouped. Can you place them into their respective sections based on their functions

flux

Got it — I’ll keep the existing pin groups and assign the terminal Section property so the symbol is organized into functional sections without duplicating pins.

flux

I assigned the existing grouped pins into functional Section values across all 72 terminals: Power, Ground, System Control, Clock, GPIO Port A/B/C/D/E, Debug/GPIO, and RTC/GPIO where appropriate.
Verification spot-checks passed:
  • VDD_1 → Section Power
  • VSS_1 → Section Ground
  • NRST → Section System Control
  • PH0-_OSC_IN → Section Clock
  • PA0 → Section GPIO Port A
  • PB3 → Section Debug / GPIO Port B
  • PC13 → Section RTC / GPIO Port C
  • PE10 → Section GPIO Port E
Review reports no open errors or warnings. Some Section values triggered non-blocking suggestions because they are more specific than Flux’s common presets, but the values were applied successfully.
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Files

Pins

Symbol

Layout

Preview

STM32U3C5JIY6QTR Pin Groups
Date: 2026-05-16
Grouping rule
Each WLCSP72 ball / schematic terminal is assigned to exactly one primary function group. Pins with multiple alternate functions are grouped by their primary datasheet pin name or most common schematic use, not duplicated across every alternate peripheral.
Exclusive groups
Power - Digital VDD

Table

TerminalBallNotes
VDD_1A1Digital supply VDD
VDD_2A15Digital supply VDD
VDD_3H2Digital supply VDD
VDD_4J13Digital supply VDD
Power - USB Supply

Table

TerminalBallNotes
VDDUSBA3USB transceiver supply
Power - Analog Supply

Table

TerminalBallNotes
VDDAH16Analog supply
Power - Core 1.1V Decoupling

Table

TerminalBallNotes
VDD11J3Core/internal regulator 1.1 V domain decoupling pin
Power - Backup Supply

Table

TerminalBallNotes
VBATB16Backup / RTC supply
Power - SMPS Supply

Table

TerminalBallNotes
VDDSMPSJ5SMPS supply input
Power - SMPS Switching Node

Table

TerminalBallNotes
VLXSMPSJ7SMPS switching inductor node
Ground - Digital VSS

Table

TerminalBallNotes
VSS_1A13Digital ground
VSS_2B2Digital ground
VSS_3H4Digital ground
VSS_4J15Digital ground
Ground - Analog VSSA

Table

TerminalBallNotes
VSSAG15Analog ground
Ground - SMPS Ground

Table

TerminalBallNotes
VSSSMPSH6SMPS ground
System Control - Reset

Table

TerminalBallNotes
NRSTF16Active-low reset input
System Control - Boot

Table

TerminalBallNotes
PH3-_BOOT0C11BOOT0 / boot mode input
Clock - HSE Oscillator

Table

TerminalBallNotes
PH0-_OSC_IND16HSE oscillator input
PH1-_OSC_OUTD14HSE oscillator output
Clock - LSE Oscillator

Table

TerminalBallNotes
PC14-_OSC32_INC15LSE 32.768 kHz oscillator input
PC15-_OSC32__OUTC13LSE 32.768 kHz oscillator output
GPIO Port A

Table

TerminalBall
PA0F14
PA1E9
PA2G13
PA3H14
PA4F12
PA5G11
PA6H12
PA7F10
PA8D2
PA9D4
PA10D6
PA11C1
PA12C3
GPIO Port A / Debug
These remain assigned once here rather than repeated under both GPIO and Debug.

Table

TerminalBallCommon debug role
PA13C5SWDIO / JTMS
PA14C7SWCLK / JTCK
PA15D8JTDI / GPIO
GPIO Port B

Table

TerminalBall
PB0G9
PB1J11
PB2H10
PB5C9
PB6D10
PB7A11
PB8B10
PB9B12
PB10G3
PB11G5
PB12J1
PB13F2
PB14F4
PB15G1
GPIO Port B / Debug
These remain assigned once here rather than repeated under both GPIO and Debug.

Table

TerminalBallCommon debug role
PB3A9JTDO / TRACESWO / GPIO
PB4B8NJTRST / GPIO
GPIO Port C

Table

TerminalBall
PC0E15
PC1D12
PC2E11
PC3E13
PC6E3
PC7E1
PC8E5
PC9E7
PC10B4
PC11B6
PC12A5
GPIO Port C / RTC-Tamper

Table

TerminalBallNotes
PC13B14GPIO / RTC tamper-capable domain pin
GPIO Port D

Table

TerminalBall
PD2A7
GPIO Port E

Table

TerminalBall
PE10G7
PE11H8
PE12J9
PE13F8
PE14F6
Verification
Total terminals grouped: 72 / 72. No terminal is intentionally listed in more than one group.
Applied component metadata
The schematic terminal components were updated with Pin Group and Pin Type properties using the same exclusive grouping above. GPIO terminals were set as Bi-Directional, power pins as Power In except VLXSMPS as Power Out, ground pins as Ground, reset/boot/oscillator inputs as Input, and oscillator outputs as Output.

  • Grouping rule

  • Exclusive groups

  • Power - Digital VDD

  • Power - USB Supply

  • Power - Analog Supply

  • Power - Core 1.1V Decoupling

  • Power - Backup Supply

  • Power - SMPS Supply

  • Power - SMPS Switching Node

  • Ground - Digital VSS

  • Ground - Analog VSSA

  • Ground - SMPS Ground

  • System Control - Reset

  • System Control - Boot

  • Clock - HSE Oscillator

  • Clock - LSE Oscillator

  • GPIO Port A

  • GPIO Port A / Debug

  • GPIO Port B

  • GPIO Port B / Debug

  • GPIO Port C

  • GPIO Port C / RTC-Tamper

  • GPIO Port D

  • GPIO Port E

  • Verification

  • Applied component metadata