Reviewed the SN65HVD75D part against the TI datasheet and created the detailed report in sn65hvd75d-part-review. The pinout, 8-pin SOIC package metadata, and symbol terminals match the datasheet; no Datasheet property update was needed because one was already set.
Open items:
Pin descriptions/types are not populated.
Datasheet URL is an uploaded official PDF, not a direct ti.com URL.
Footprint pad dimensions could not be fully verified from available layout data.
Suggested next steps:
Add pin descriptions and pin types to the terminals.
Replace the Datasheet URL with a direct TI URL if desired.
Perform a dimensional footprint check against TI’s D0008A SOIC land pattern.
I’ll update each terminal with the datasheet-backed pin description and electrical pin type, then inspect the schematic to confirm the metadata is present.
The part already had a Datasheet URL set, so no Datasheet property update was required. The loaded datasheet is a Texas Instruments SN65HVD72/SN65HVD75/SN65HVD78 datasheet, document SLLSE11C, March 2012 revised September 2013.
Datasheet key specifications for SN65HVD75D
Function: 3.3 V half-duplex RS-485/RS-422 differential bus transceiver with separate driver enable and receiver enable.
Supply voltage recommended operating range: 3.0 V to 3.6 V, nominal 3.3 V.
Signaling rate for SN65HVD75: up to 20 Mbps.
Cable length guide: up to 100 m for HVD75 family member.
Bus topology: half-duplex two-wire bus.
Node loading: supports up to 256 nodes.
Logic inputs: 5 V tolerant; VIH min 2.0 V, VIL max 0.8 V.
Bus common-mode/input range, recommended: -7 V to +12 V.
Differential input voltage range: -12 V to +12 V.
Receiver hysteresis: 50 mV min, 80 mV typical.
Receiver failsafe: output high for open, shorted, or idle bus states.
The symbol terminals and pin numbers match the TI datasheet pin configuration for the 8-pin D package. The left/right placement is also reasonable: logic/control pins R, ~RE, DE, D are on one side and bus/power pins A, B, GND, VCC are on the other.
Footprint review
The footprint contains 8 pads named according to the schematic terminals and includes SOIC-style silkscreen/fab geometry. The package metadata says 8-SOIC, matching the SN65HVD75D orderable device. However, the available layout inspection did not expose pad dimensions, pad pitch, or toe/heel geometry, so the footprint could only be checked at the package/pad-count/name level, not fully dimensionally validated against TI's D0008A land pattern.
Mismatches / issues flagged
No pin descriptions are populated on the Flux terminals; each terminal currently only has Pin Type: Unspecified and Pin Number. Add Pin Description/Pin Type metadata for better library quality.
The Datasheet URL is set, but it points to a stored uploaded PDF rather than a direct ti.com URL. This is acceptable if the PDF is official and stable, but a direct TI product datasheet URL would be preferable for traceability.
Footprint dimensional verification is incomplete because pad geometry details were not available from the layout inspection output.
Recommended property cleanup
Add these terminal descriptions/types:
R, pin 1: Receiver output, output
~RE, pin 2: Receiver enable input, active low, input
DE, pin 3: Driver enable input, input
D, pin 4: Driver data input, input
GND, pin 5: Ground, power
A, pin 6: Non-inverting RS-485/RS-422 bus terminal, bidirectional/differential bus
B, pin 7: Inverting RS-485/RS-422 bus terminal, bidirectional/differential bus