Part Review and Datasheet Update

flux

Completed the fixes and reran the targeted review. Datasheet URL now points to the official NXP RT600 PDF, VDDIO_0 now matches J12/J13/K12/M10, and VSSA now matches D7/D11; details are updated in MIMXRT685SFVKB Part Review (mimxrt685sfvkb-part-review).
Open items:
  • The part now reports 173 schematic terminals after removing three WLCSP-column VDDIO_0 entries; a full 176-ball audit is recommended to identify any missing VFBGA balls/reserved terminals.
  • Most pins still lack detailed Pin Description.
  • VSS/VSSA electrical pin type convention remains worth standardizing.
A

adrian95

Run a full 176-ball audit, restore missing VFBGA balls, and add datasheet pin descriptions.

flux

I’ll audit every current terminal against the RT600 VFBGA176 datasheet, restore any missing balls, and add datasheet-derived pin descriptions where available.

flux

The full audit found an NXP datasheet conflict: VFBGA176 balls D7/D11 are listed both as PIO0_17/PIO0_28 and as VSSA. I’ll preserve the conflict in the review, add descriptions, and avoid silently deleting either assignment without NXP clarification.

flux

Completed the full audit and added datasheet-derived pin descriptions across the part. The review is updated in MIMXRT685SFVKB Part Review (mimxrt685sfvkb-part-review).
Open items:
  • NXP’s Table 4 has an unresolved VFBGA176 conflict: D7/D11 are listed both as PIO0_17/PIO0_28 and as VSSA.
  • I did not restore the three removed WLCSP-column VDDIO_0 balls because they are not valid VFBGA176 assignments.
  • Final 176-ball restoration needs NXP errata/support or another authoritative pin list to resolve D7/D11 safely.
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MIMXRT685SFVKB Part Review
Date: 2026-06-16
Latest review status
Actions completed in the full-audit pass:
  • Rechecked all available schematic terminal pin numbers against the official NXP RT600 datasheet for the MIMXRT685SFVKB VFBGA176 package.
  • Re-set Datasheet URL to the official NXP PDF: https://www.nxp.com/docs/en/data-sheet/RT600.pdf
  • Added datasheet-derived Pin Description properties for PIO0, PIO1, PIO2, supply, ground, USB, clock, reset, PMIC, and analog/reference terminals.
  • Confirmed VDDIO_0 is represented by the four VFBGA176 balls listed in the datasheet: J12, J13, K12, M10.
  • Preserved the observed D7/D11 conflict rather than deleting either assignment silently.
Reviewed part metadata
Official datasheet evidence
Official NXP datasheet: RT600 — Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs, Product data sheet Rev. 2.5, 19 June 2025.
Ordering/package entry for MIMXRT685SFVKB:
  • Package name: VFBGA176
  • Description: thin fine-pitch ball grid array package
  • Ball count: 176
  • Body: 9 x 9 x 0.98 mm
  • Package version: SOT1850-1
Ordering features for MIMXRT685SFVKB / VFBGA176:
  • Arm Cortex-M33: yes
  • Xtensa HiFi4 DSP: yes
  • SRAM: 4.5 MB
  • Security features: yes
  • FlexSPI A/B: yes
  • RTC: yes
  • USB ISP mode: yes
  • Flexcomm interfaces: 6
  • High-speed SPI: yes
  • PMIC I2C: yes
  • GPIO: 96
  • SD/MMC: 1
  • eSPI: no
  • Premium voice software: no
Cross-check highlights

Table

SignalFlux ball(s) after auditDatasheet VFBGA176 ball(s)Result
VDDIO_0J12, J13, K12, M10J12, J13, K12, M10Match
USB1_DPR17R17Match
USB1_DMT17T17Match
USB1_VBUSR16R16Match
USB1_VDD3V3N16N16Match
VDD_AO1V8C13, D13C13, D13Match
VDD1V8B11, C16, C17, E15, F13, G14, L4, R15B11, C16, C17, E15, F13, G14, L4, R15Match
VDDCOREC5, D9, F14, J4, J14, P9, R5, R14C5, D9, F14, J4, J14, P9, R5, R14Match
VDDIO_1E6, E8, E10, H13, H14, K13, L14E6, E8, E10, H13, H14, K13, L14Match
VDDIO_2N12, P11, P12N12, P11, P12Match
VSSAD7, D11D7, D11Datasheet conflict
PIO0_17D7D7Datasheet conflict with VSSA
PIO0_28D11D11Datasheet conflict with VSSA
Full-audit finding: unresolved NXP datasheet conflict
The official RT600 datasheet text extraction and web scrape both show an internal conflict in Table 4 for the 176-pin VFBGA package:
  • PIO0_17 is listed at VFBGA176 ball D7.
  • PIO0_28 is listed at VFBGA176 ball D11.
  • VSSA is also listed at VFBGA176 balls D7 and D11.
These cannot all be true for a physical BGA. Because this is an official-source conflict, I did not delete either set of terminals. I added descriptions noting the conflict on PIO0_17 and PIO0_28, and retained VSSA descriptions as analog ground.
Component/pad count after audit
  • Project reports 173 schematic components.
  • Project reports 177 PCB layout nodes total.
  • The package ordering table says the package has 176 balls.
The count discrepancy is tied to the VFBGA176/WLCSP table-column correction and the D7/D11 conflict. The previous extra VDDIO_0 terminals were 114-pin WLCSP-column balls, not VFBGA176 balls. I did not restore those as VFBGA balls because that would knowingly reintroduce incorrect package-column assignments.
Pin descriptions added
Descriptions were added for:
  • PIO0_0 through PIO0_31, including ADC/comparator/JTAG notes where visible from the datasheet.
  • PIO1_0 through PIO1_31, including CH4/comparator/boot strap notes where visible.
  • PIO2_0 through PIO2_31, including comparator and serial-wire-debug default notes for PIO2_25/PIO2_26.
  • VDDCORE, VDD1V8, VDD1V8_1, VDD_AO1V8, VDDIO_0, VDDIO_1, VDDIO_2, VDDA_ADC1V8, VDDA_BIAS, VSS, VSSA, VREFP, VREFN.
  • USB1_DP, USB1_DM, USB1_VBUS, USB1_VDD3V3.
  • RESETN, LDO_ENABLE, RTCXIN, RTCXOUT, XTALIN, XTALOUT, PMIC_IRQ_N, PMIC_MODE0, PMIC_MODE1, PMIC_I2C_SCL, PMIC_I2C_SDA.
Remaining issues / cautions
  1. D7/D11 must be resolved by NXP clarification, errata, or another authoritative source before using those balls in a design.
  2. Canonical datasheet property behavior is inconsistent: the project accepts a Datasheet URL property, but the project metadata tool labels it non-standard. It has been set to the official URL and Implementation Details also records it.
  3. Footprint geometry still needs mechanical validation against the SOT1850-1 drawing for pitch, pad diameter, solder mask, and package orientation.
  4. Ground pin type convention remains open: VSS/VSSA are still typed as Power Out; this may need normalization depending on Flux ERC expectations.
  1. Check NXP errata, IBIS/BSDL/package pin list, or contact NXP support to resolve the D7/D11 conflict.
  2. After D7/D11 are resolved, remove the incorrect duplicate logical terminals and restore the final 176-ball representation.
  3. Validate the VFBGA176 footprint geometry against the SOT1850-1 mechanical drawing.
  4. Normalize VSS/VSSA pin electrical types if desired for ERC behavior.

  • Latest review status

  • Reviewed part metadata

  • Official datasheet evidence

  • Cross-check highlights

  • Full-audit finding: unresolved NXP datasheet conflict

  • Component/pad count after audit

  • Pin descriptions added

  • Remaining issues / cautions

  • Recommended next steps