# ADC09SJ1300AAVT (Component) ## Description Analog to Digital Converters - ADC Single-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface 144-FCBGA -40 to 85 ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltagecontrolled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. Features • ADC Core: – Resolution: 9 Bit – Maximum sampling rate: 1.3GSPS – Non-interleaved architecture – Internal dither reduces high-order harmonics • Performance specifications (–1dBFS): – SNR (100 MHz): 53.5dBFS – ENOB (100 MHz): 8.5 Bits – SFDR (100 MHz): 64dBc – Noise floor (–20dBFS): –143dBFS • Full-scale input voltage: 80 mVPP-DIFF • Full-power input bandwidth: 6GHz • JESD204C Serial data interface: – Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes – Maximum baud-rate: 17.16Gbps – 64B/66B and 8B/10B encoding modes – Subclass-1 support for deterministic latency – Compatible with JESD204B receivers • Optional internal sampling clock generation – Internal PLL and VCO (7.2–8.2GHz) • SYSREF Windowing eases synchronization • Four clock outputs simplify system clocking – Reference clocks for FPGA or adjacent ADC – Reference clock for SerDes transceivers • Timestamp input and output for pulsed systems • Power consumption (1GSPS): – Quad Channel: 450mW / channel – Dual channel: 625mW / channel – Single channel: 940mW • Power supplies: 1.1V, 1.9V #CommonPartsLibrary #IntegratedCircuit #ADC #HighSpeedADC #RFADC #JESD204C #13GSPS #9bitADC #DirectRFSampling #TexasInstruments #MixedSignal #DataAcquisition #JESD204 ## Component Details - **Owner:** adrian95 - **Created:** 6/10/2026 - **Last Updated:** 6/10/2026 - **Visibility:** Public - **License:** https://creativecommons.org/licenses/by/4.0/ - **Part Type:** Integrated Circuits - **Datasheet URL:** https://storage.googleapis.com/graviton-electric-symbols/document_assets/user-uploaded/6861e2290d8ac90239799096a3bdb6fcb2bfe6d934982851167fc205d34b9fac.pdf - **Symbol Style:** parametric-v1 - **Implementation Details:** Official datasheet: https://www.ti.com/lit/ds/symlink/adc09sj1300.pdf - **Package or Case Code:** TO - **Manufacturer Part Number:** ADC09SJ1300AAVT - **Manufacturer Name:** Texas Instruments - **Part Type:** Integrated Circuits - **Sub-Type:** Logic - **Manufacturer:** Texas Instruments - **MPN:** ADC09SJ1300AAVT - **Mount Type:** PCB - **Package / Case Code:** FPGA - **Pin Count:** 144 - **Logic Function:** AND ## Pins | Pin | Name | Type | |-----|------|------| | A1 | AGND_1 | | | A2 | INA+ | | | A3 | INA- | | | A4 | AGND_2 | | | A5 | AGND_3 | | | A6 | DNC_1 | | | A7 | DNC_2 | | | A8 | AGND_4 | | | A9 | CALTRIG | | | A10 | VD11_1 | | | A11 | DGND_1 | | | A12 | DGND_2 | | | B1 | AGND_5 | | | B2 | AGND_6 | | | B3 | AGND_7 | | | B4 | AGND_8 | | | B5 | AGND_9 | | | B6 | AGND_10 | | | B7 | AGND_11 | | | B8 | AGND_12 | | | B9 | CALSTAT | | | B10 | VD11_2 | | | B11 | DGND_3 | | | B12 | DGND_4 | | | C1 | TMSTP+ | | | C2 | AGND_13 | | | C3 | BG | | | C4 | ~SYNCSE | | | C5 | AGND_14 | | | C6 | AGND_15 | | | C7 | CLKCFG0 | | | C8 | PLLREF_SE | | | C9 | ORA | | | C10 | DGND_5 | | | C11 | DNC_3 | | | C12 | D3+ | | | D1 | TMSTP- | | | D2 | AGND_16 | | | D3 | AGND_17 | | | D4 | VA19_1 | | | D5 | VA19_2 | | | D6 | VA11_1 | | | D7 | CLKCFG1 | | | D8 | PLL_EN | | | D9 | ORB | | | D10 | VD11_3 | | | D11 | DNC_4 | | | D12 | D3- | | | E1 | AGND_18 | | | E2 | AGND_19 | | | E3 | VA11_2 | | | E4 | AGND_20 | | | E5 | VA11_3 | | | E6 | VA19_3 | | | E7 | AGND_21 | | | E8 | ~SCS | | | E9 | ORC | | | E10 | VD11_4 | | | E11 | DNC_5 | | | E12 | D2+ | | | F1 | CLK+ | | | F2 | SE_CLK | | | F3 | VA11_4 | | | F4 | AGND_22 | | | F5 | VA11_5 | | | F6 | VA19_4 | | | F7 | AGND_23 | | | F8 | SCLK | | | F9 | ORD | | | F10 | DGND_6 | | | F11 | DNC_6 | | | F12 | D2- | | | G1 | CLK- | | | G2 | SE_GND | | | G3 | VA11_6 | | | G4 | AGND_24 | | | G5 | VA11_7 | | | G6 | VA19_5 | | | G7 | AGND_25 | | | G8 | SDI | | | G9 | SDO | | | G10 | DGND_7 | | | G11 | DNC_7 | | | G12 | D1+ | | | H1 | AGND_26 | | | H2 | AGND_27 | | | H3 | VA11_8 | | | H4 | AGND_28 | | | H5 | VA11_9 | | | H6 | VA19_6 | | | H7 | AGND_29 | | | H8 | VD11_5 | | | H9 | VD11_6 | | | H10 | VD11_7 | | | H11 | DNC_8 | | | H12 | D1- | | | J1 | SYSREF+ | | | J2 | AGND_30 | | | J3 | PGND_1 | | | J4 | VPLL19_1 | | | J5 | VPLL19_2 | | | J6 | VA11_10 | | | J7 | PLLREFO+ | | | J8 | VTRIG_1 | | | J9 | TRIGOUT+ | | | J10 | VD11_8 | | | J11 | DNC_9 | | | J12 | D0+ | | | K1 | SYSREF- | | | K2 | AGND_31 | | | K3 | TDIODE+ | | | K4 | TDIODE- | | | K5 | PGND_2 | | | K6 | VREFO | | | K7 | PLLREFO- | | | K8 | VTRIG_2 | | | K9 | TRIGOUT- | | | K10 | DGND_8 | | | K11 | DNC_10 | | | K12 | D0- | | | L1 | AGND_32 | | | L2 | AGND_33 | | | L3 | AGND_34 | | | L4 | AGND_35 | | | L5 | AGND_36 | | | L6 | AGND_37 | | | L7 | AGND_38 | | | L8 | AGND_39 | | | L9 | DGND_9 | | | L10 | VD11_9 | | | L11 | DGND_10 | | | L12 | DGND_11 | | | M1 | AGND_40 | | | M2 | DNC_11 | | | M3 | DNC_12 | | | M4 | AGND_41 | | | M5 | AGND_42 | | | M6 | DNC_13 | | | M7 | DNC_14 | | | M8 | AGND_43 | | | M9 | PD | | | M10 | VD11_10 | | | M11 | DGND_12 | | | M12 | DGND_13 | | --- *Generated from [https://www.flux.ai/adrian95/adc09sj1300aavt](https://www.flux.ai/adrian95/adc09sj1300aavt)*