ESP32 Mini Drone Flight Controller Design
Worked for 4 mins 57 sec
I’m blocked because credits ran out just before I could run the final post-placement review.
Completed this session:
- Continued PCB placement on the existing 50 × 50 mm, 4-layer board.
- Corrected the mislabeled duplicate ground-like net for the GPIO8/status LED path to ESP_GPIO8_LED_BOOT before placement.
- Placed all 29 physical components by functional block.
- Enhanced placement for compactness and robustness:
- ESP32-C3 module is now fully inside the board with antenna side at the top edge.
- BMI270 IMU is kept central for better motion sensing.
- TPS63001 power stage is compact around U3/L3/C4/C5/C6/C7/J1.
- LiPo, motor, GPS/UART, programming headers, and reset/boot buttons remain edge-accessible.
- Decoupling and strap components remain close to their IC pins.
- LED parts were moved away from the ESP32 antenna area.
- UART programming header was moved closer to the ESP32 to reduce long UART paths.
- Placement tool reported no overlap, off-board, unplaced, spacing, or critical placement problems after the final correction.
Still required:
- Re-run post-placement review.
- Confirm only expected unrouted-airwire issues remain.
- Fix any actual placement/clearance issues if found.
- Ask for your approval before routing traces.
Run ERC/DRC
Check antenna clearance
Optimize power loop
Inspect edge access
Refine this doc
Ask about this doc
Board Bring-Up Plan — ESP32 Mini Drone Flight Controller
Prerequisites
- Equipment: current-limited bench supply or protected 1S LiPo source, multimeter, oscilloscope if available, USB-UART adapter, PlatformIO workstation, GPS module if testing return-to-home expansion, and a logic analyzer if available.
- Firmware reference: Firmware Starter
- Safety: perform all motor-output tests with propellers removed. Start with a current limit of 100 mA, then increase only after the 3.3 V rail is verified.
1. Visual Inspection
- Check U1 ESP32-C3-MINI-1U-N4, U2 BMI270, and U3 TPS63001DRCR orientation.
- Confirm J1 LiPo connector polarity: J1 P1 = VBAT, J1 P2 = GND.
- Inspect U3 power components: L3 = 2.2 µH, C4 = 10 µF input, C5/C6 = 10 µF output capacitors, C7 = 100 nF VOUT bypass.
- Confirm no solder bridges on U1 ground pads, U2 LGA/QFN-style pads, and U3 exposed pad.
2. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Tolerance | Measure At | Initial Current Limit | Pass Criteria |
|---|---|---|---|---|---|---|
| VBAT | J1 P1 LiPo input | 3.0–4.2 V | Source dependent | J1 P1 to GND | 100 mA first power-on | No short; voltage present at U3 VIN/VINA |
| 3V3 | U3 TPS63001 VOUT | 3.3 V | ±5% bring-up limit | C5 P1/C6 P1/C7 P1, U1 3V3, J4 pin 3, J3 pin 3 | 100 mA then 500 mA | 3.135–3.465 V and no overheating |
| VBAT_SENSE | R5/R6 divider | VBAT × 220k/(470k+220k) | ±10% | U1 GPIO0 / C8 P1 | N/A | 4.2 V input reads about 1.34 V |
Procedure:
- With no battery connected, measure resistance from VBAT to GND and 3V3 to GND; investigate very low resistance before applying power.
- Apply 3.7 V to J1 with 100 mA current limit.
- Verify U3 output is near 3.3 V before connecting USB-UART or external GPS modules.
- Increase current limit to 500 mA only after the rail is stable.
- Check 3V3 ripple at C5/C6 with an oscilloscope if available.
3. Critical Signal Verification
Table
| Signal | Net Name | Expected State | Measure At | Notes |
|---|---|---|---|---|
| ESP32 enable | ESP_EN | High near 3.3 V after startup | U1 EN, R1 P2, SW1 P1 | SW1 should pull low to reset |
| Boot mode | ESP_BOOT | High normally; low when SW2 pressed | U1 GPIO9, R2 P2 | Hold low during reset to enter bootloader |
| GPIO2 strap | ESP_GPIO2_STRAP | Pulled high by R8 | U1 GPIO2, R8 P2 | Boot stability strap |
| GPIO8 LED/strap | ESP_GPIO8_LED_BOOT | Pulled high by R9; firmware can pull low for LED | U1 GPIO8, D1 cathode | Active-low LED path via R7/D1 |
| I2C SDA | I2C_SDA | Idle high at 3.3 V | U1 GPIO4, U2 SDX | R3 pull-up |
| I2C SCL | I2C_SCL | Idle high at 3.3 V | U1 GPIO5, U2 SCX | R4 pull-up |
| IMU INT1 | IMU_INT1 | Firmware-dependent | U1 GPIO3, U2 INT1 | Used for BMI270 interrupt/data-ready |
4. Connector and Interface Tests
Table
| Connector | Type | Pins to Verify | Test Method |
|---|---|---|---|
| J1 | 2-pin JST-PH LiPo input | P1 VBAT, P2 GND | Polarity and continuity check before power |
| J2 | 4-pin JST-SH motor logic outputs | P1 MOTOR1, P2 MOTOR2, P3 MOTOR3, P4 MOTOR4 | Use firmware PWM test with propellers removed |
| J3 | 4-pin JST-SH GPS/UART expansion | P1 GPS_RX_TO_ESP, P2 GPS_TX_FROM_ESP, P3 3V3, P4 GND | Loopback or GPS NMEA serial test at 9600 baud |
| J4 | 4-pin JST-SH programming/log header | P1 UART0_TX, P2 UART0_RX, P3 3V3, P4 GND | USB-UART serial monitor and flashing test |
5. Programming and Debug Interface
Table
| Interface | Signals | Connector | Tool |
|---|---|---|---|
| ESP32 UART bootloader/debug | UART0_TX, UART0_RX, 3V3, GND, BOOT/SW2, RESET/SW1 | J4 + buttons | PlatformIO / esptool.py |
Procedure:
- Connect USB-UART at 3.3 V logic only: J4 P1 to adapter RX, J4 P2 to adapter TX, J4 P4 to GND.
- Hold SW2, tap SW1, then release SW2 to enter bootloader.
- Run
pio run -t uploadusing the firmware starter project. - Run
pio device monitor -b 115200and confirm startup text.
6. Functional Validation
Table
| Test | Components Involved | Input | Expected Output | Pass Criteria |
|---|---|---|---|---|
| 3.3 V regulator startup | J1, U3, L3, C4/C5/C6/C7 | 3.0–4.2 V at VBAT | 3.3 V rail | Stable 3V3, no thermal issue |
| ESP32 boot | U1, R1, C2, SW1/SW2, J4 | Power + serial connection | Boot log at 115200 baud | Firmware starts reliably |
| BMI270 I2C detection | U1, U2, R3/R4, C3/C9 | Firmware I2C scan/init | BMI270 detected at 0x68 | IMU telemetry prints IMU=ok |
| Battery ADC | U1 GPIO0, R5/R6/C8 | Known VBAT voltage | Reported VBAT close to expected | Within ±10% before calibration |
| Status LED | U1 GPIO8, R7, D1, R9 | Firmware toggles LED | LED blinks/turns on | Active-low control works |
| Motor outputs | U1 GPIO1/6/7/10, J2 | Safe PWM test | PWM visible on J2 pins | No props attached; correct pins toggle |
| GPS/UART expansion | U1 GPIO18/19, J3 | GPS module or UART loopback | NMEA or echoed data | Serial data visible in monitor |
| Low-battery behavior | Firmware + VBAT_SENSE | Lower bench supply slowly | Warning/failsafe behavior | LED warning and emergency landing hook triggers |
7. Expected Measurements Reference
Table
| Measurement | Location | Expected Value | Tolerance | Instrument |
|---|---|---|---|---|
| 3V3 rail | C5 P1 to GND | 3.3 V | ±5% bring-up | Multimeter |
| VBAT divider at 4.2 V input | C8 P1 / U1 GPIO0 | ~1.34 V | ±10% | Multimeter |
| I2C idle high | U2 SDX/SCX | 3.3 V | ±10% | Multimeter/oscilloscope |
| EN idle | U1 EN | 3.3 V | ±10% | Multimeter |
| BOOT button pressed | U1 GPIO9 | <0.3 V | N/A | Multimeter |
| Motor PWM | J2 P1–P4 | 0–3.3 V PWM | Firmware-dependent | Oscilloscope/logic analyzer |
Pass/Fail Summary
Table
| Test Section | Result | Notes |
|---|---|---|
| Visual Inspection | [ ] Pass / [ ] Fail | |
| Power Rails | [ ] Pass / [ ] Fail | |
| Critical Signals | [ ] Pass / [ ] Fail | |
| Connectors | [ ] Pass / [ ] Fail | |
| Programming | [ ] Pass / [ ] Fail | |
| Functional Validation | [ ] Pass / [ ] Fail |
Board Status: [ ] Ready for flight testing without props / [ ] Requires rework
Open Bring-Up Risks
- Motor outputs are logic-level control lines only; confirm the external ESC/driver input voltage and timing before connecting motors.
- Return-to-home depends on an external GPS on J3 and firmware support beyond this starter.
- The first powered motor tests must be done with propellers removed.
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Connector and Interface Tests
5. Programming and Debug Interface
6. Functional Validation
7. Expected Measurements Reference
Pass/Fail Summary
Open Bring-Up Risks
