Project Specification in Markdown

flux

I can’t run analysis or auto-layout right now because the account has no available ACUs, so AI execution features are unavailable.
What has been completed so far:
  • Step 1 schematic was implemented: STM32F427ZI, KSZ8895 Ethernet switch with 4 RJ45 MagJack ports, master CAN, isolated slave CAN, J8 5V input, 3.3V rail, isolated 5V CAN rail, and SWD.
  • Floating-pin/ERC cleanup was completed for the checked categories.
  • Documentation was created/updated for Step 1 implementation, firmware starter, and bring-up plan.
What remains:
  • Run PCB placement analysis and auto-layout once ACUs are available.
  • Determine whether placement, routing, or both are needed from the current PCB state.
  • Apply placement/routing, then run DRC/airwire checks.
  • Review thermal risk of the 3.3V LDO and verify KSZ8895 strap/clock details before manufacturing.
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aassaaff

flux

I can’t run PCB analysis or auto-layout at the moment because there are no available ACUs on the account, so AI execution features are unavailable.
Current state from this session:
  • Step 1 schematic was created for STM32F427ZI, KSZ8895 Ethernet switch, 4 RJ45 MagJack ports, master CAN, isolated slave CAN, J8 5V input, local 3.3V, isolated 5V, and SWD.
  • Floating-pin/ERC cleanup was completed using common defaults.
  • Step 1 review, firmware starter, and bring-up documents were created.
Still needed once ACUs are available:
  • Inspect current PCB placement/routing state.
  • Decide whether auto-placement, auto-routing, or both are required.
  • Apply auto-layout results.
  • Run DRC/airwire checks and fix critical issues.
  • Recheck 3.3V regulator thermal load and KSZ8895 reference-design details before manufacturing.
Review layout later
Document blockers
Check BOM readiness
Inspect PCB state
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Schematic

Layout

3D View

Step 1 Schematic Implementation Plan — MCU + Ethernet + CAN
Purpose
This document defines the detailed schematic implementation plan for Step 1 of the CT04 Control PCB. It is a planning document only; no components should be added until the user approves this plan.
Step 1 scope:
  • STM32F427ZI MCU base circuit.
  • Local logic power required for Step 1.
  • KSZ8895 Ethernet switch with four external RJ45 ports using integrated magnetics.
  • RMII connection between STM32 Ethernet MAC and KSZ8895.
  • Two CAN interfaces: slave CAN uses ISO1042 isolation; master CAN is non-isolated.
  • RJ45 CAN connectors with the confirmed CT04 pinout.
  • 5V for Step 1 comes from J8. The slave CAN isolated side uses isolated 5V generated from J8 5V on the Control PCB.
Out of Step 1 scope:
  • LoRa and Wi‑Fi.
  • USB hub and USB connectors.
  • RS‑485/BMS.
  • 24V/5V load gating outputs.
  • Fans, lights, sensors, panel interface.
  • STO safety circuit.
  • Full PCB placement/routing.
Confirmed User Decisions

Table

TopicDecision
Main MCUSTM32F427ZI, 144-pin LQFP
Ethernet switchKSZ8895 family, 5-port switch
Ethernet topology4 external switch ports + 1 MCU uplink
MCU ↔ switch interfaceRMII
External Ethernet connectorsRJ45 connectors with integrated magnetics
CAN physical connectorRJ45
CAN RJ45 pinoutPin 1 = CAN_H, pin 2 = CAN_L, pin 3 = GND
Master CAN termination120Ω required
Slave CAN terminationNo termination
CAN isolation referenceTI ISO1042DWEVM / ISO1042-based design for slave CAN only
ISO1042 quantity1 unit for slave CAN
Master CANNon-isolated CAN transceiver
Isolated CAN supplyIsolated 5V generated locally on Control PCB from J8 5V
Library partsUse suitable common Flux/library parts where exact MPN is not specified
Control PCB power architectureControl PCB receives regulated rails from Power PCB; it does not implement 54.6V DC/DC conversion
Step 1 Functional Block Diagram
Diagram



  
    
  
  
    
  





























"5V from Power PCB"
"5V input protection / filtering"
"3.3V regulator for MCU + Ethernet logic"
"Isolated node_5V DC/DC for slave CAN field side"
"STM32F427ZI"
"KSZ8895 Ethernet Switch"
"CAN transceiver logic sides"
"RJ45 Mag Port 1"
"RJ45 Mag Port 2"
"RJ45 Mag Port 3"
"RJ45 Mag Port 4"
ISO_CAN_SLAVE
CAN_MASTER
"RJ45 Master CAN\n120Ω termination"
"RJ45 Slave CAN\nNo termination"
Schematic Pages / Functional Sections
Sheet 1 — Step 1 Power Entry and Local Rails
Create the minimum power infrastructure needed for Step 1 only.
Planned circuits:
  1. 5V input net from J8 / Power PCB connector.
  2. 5V protection/filtering placeholder:
    • input bulk capacitor,
    • local bypass capacitors,
    • fuse/current limit and TVS to be finalized when full power connector is implemented.
  3. 3.3V regulator from 5V for:
    • STM32 VDD/VDDA,
    • KSZ8895 logic power as required by datasheet,
    • ISO1042 logic-side VCC1,
    • RMII pullups/straps as required.
  4. Isolated 5V DC/DC from J8 5V for slave ISO1042 VCC2 / isolated bus side.
  5. Separate net names:
    • +5V_IN
    • +3V3
    • +5V_ISO_CAN
    • GND
    • GND_CAN_ISO
Implementation notes:
  • Do not connect GND and GND_CAN_ISO directly.
  • Provide clear isolation barrier between logic ground and isolated CAN ground.
  • Use one isolated 5V supply sized for the slave ISO1042 bus side.
  • Add test points for +5V_IN, +3V3, +5V_ISO_CAN, GND, and GND_CAN_ISO.
Sheet 2 — STM32F427ZI Core
Use STM32F427ZI reference design/datasheet as source.
Planned circuits:
  1. MCU power:
    • all VDD pins to +3V3,
    • all VSS pins to GND,
    • VDDA/VREF+ filtering from +3V3,
    • VSSA to analog ground reference per STM32 reference guidance.
  2. Decoupling:
    • 100nF close to every VDD/VDDA supply pin,
    • several bulk capacitors near the MCU supply cluster.
  3. Clocking:
    • HSE 8MHz crystal with load capacitors unless a different KSZ8895/RMII clock strategy requires a shared oscillator.
    • LSE 32.768kHz crystal for RTC if still required.
  4. Reset/boot:
    • NRST pullup/cap/reset access per STM32 recommendation,
    • BOOT0 strap to default application boot,
    • BOOT configuration accessible for recovery if desired.
  5. Programming/debug:
    • SWD connector with SWDIO, SWCLK, NRST, GND, and target voltage reference.
  6. Ethernet RMII pins:
    • reserve STM32 Ethernet RMII signals to KSZ8895.
  7. CAN pins:
    • assign two bxCAN interfaces to ISO1042 transceivers.
Proposed STM32 interface net groups:

Table

FunctionNet Group
RMIIETH_RMII_*
Ethernet managementETH_MDIO, ETH_MDC, switch reset/interrupt/strap pins as required
CAN masterCAN_MASTER_TX, CAN_MASTER_RX
CAN slaveCAN_SLAVE_TX, CAN_SLAVE_RX
DebugSWDIO, SWCLK, NRST, SWO optional
ClocksHSE_IN, HSE_OUT, LSE_IN, LSE_OUT
Sheet 3 — KSZ8895 Ethernet Switch
Use Microchip KSZ8895 datasheet/reference/eval schematic as source.
Planned circuits:
  1. KSZ8895 power rails and decoupling:
    • implement all required analog/digital/core supply pins per exact KSZ8895 variant.
    • verify whether any rail requires 1.8V/1.2V or whether selected variant provides internal regulation.
  2. RMII host port to STM32:
    • connect RMII signals between STM32 and KSZ8895.
    • include required series resistors if recommended.
  3. Clocking:
    • define whether RMII reference clock is generated by KSZ8895, STM32/MCO, or external 50MHz oscillator.
    • this must be confirmed by datasheet/reference schematic before implementation.
  4. Four external Ethernet PHY ports:
    • each port routed to RJ45 connector with integrated magnetics.
    • include Bob Smith termination / center tap termination / common-mode components exactly as recommended for the selected integrated-magnetics connector and KSZ8895 reference design.
  5. Configuration straps:
    • mode straps for RMII, PHY address, LED behavior, unmanaged switch defaults, etc.
  6. Management/control:
    • MDIO/MDC or SPI/I2C management interface if required by selected KSZ8895 variant.
    • reset pin from STM32 or RC reset supervisor.
    • optional interrupt/status to STM32.
  7. Ethernet ESD:
    • TVS/ESD protection appropriate for Ethernet lines and chassis/earth strategy.
Ethernet open items to confirm during implementation research:
  • Exact KSZ8895 variant and package available in Flux library.
  • Exact power rails required by that variant.
  • RMII clock ownership and 50MHz reference-clock topology.
  • Exact integrated-magnetics RJ45 part number and footprint.
  • Whether connector shield connects to chassis, digital ground via RC/TVS, or left as mechanical shield pending enclosure grounding plan.
Sheet 4 — CAN Interfaces
Use TI ISO1042DWEVM and ISO1042 datasheet/reference schematic as source for the isolated slave CAN. Use a common non-isolated CAN transceiver reference design for master CAN.
Planned circuits:
  1. Two CAN channels:
    • CAN_MASTER: non-isolated CAN transceiver.
    • CAN_SLAVE: ISO1042-based isolated CAN transceiver.
  2. Slave CAN ISO1042 logic side:
    • VCC1 from +3V3 if ISO1042 variant supports 3.3V logic side; otherwise use the datasheet-required rail.
    • logic ground to GND.
    • TXD/RXD to STM32 CAN TX/RX pins.
  3. Slave CAN isolated bus side:
    • VCC2 from +5V_ISO_CAN.
    • isolated ground to GND_CAN_ISO.
  4. CAN connectors:
    • RJ45 master CAN connector: pin 1 CAN_H, pin 2 CAN_L, pin 3 GND.
    • RJ45 slave CAN connector: pin 1 CAN_H, pin 2 CAN_L, pin 3 GND_CAN_ISO.
  5. Termination:
    • master CAN: fixed 120Ω across CAN_H/CAN_L.
    • slave CAN: no termination installed.
  6. Protection:
    • CAN bus TVS diode on isolated side.
    • optional common-mode choke if recommended by reference design/noise environment.
  7. Isolation barrier:
    • no copper crossing between GND and GND_CAN_ISO except inside isolation-rated components.
    • maintain creepage/clearance per ISO1042 and isolated DC/DC ratings.
Implementation note:
  • User clarified: only slave CAN is isolated. Master CAN is non-isolated and uses the main board ground.
Sheet 5 — Connectors, Test Points, and Bring-Up Aids
Planned items:
  1. SWD debug connector.
  2. Four RJ45 Ethernet connectors with integrated magnetics.
  3. Two RJ45 CAN connectors.
  4. Power and signal test points:
    • +5V_IN, +3V3, +5V_ISO_CAN, GND, GND_CAN_ISO, NRST.
    • RMII reference clock test point if routing/layout permits.
    • CAN_H/CAN_L optional test points near each transceiver.
  5. Status LEDs, only if not conflicting with later panel/LED design:
    • 3.3V power LED optional.
    • Ethernet switch status LEDs preferably routed to RJ45 integrated LEDs or later front-panel indicators.
Proposed Net Naming

Table

DomainNet Names
Main power+5V_IN, +3V3, GND
CAN isolated power+5V_ISO_CAN, GND_CAN_ISO
Ethernet RMIIETH_RMII_REFCLK, ETH_RMII_TXD0, ETH_RMII_TXD1, ETH_RMII_TXEN, ETH_RMII_RXD0, ETH_RMII_RXD1, ETH_RMII_CRS_DV, ETH_RMII_RXER
Ethernet managementETH_MDIO, ETH_MDC, ETH_RST_N, ETH_INT_N
CAN master logicCAN_MASTER_TX, CAN_MASTER_RX
CAN master busCAN_MASTER_H, CAN_MASTER_L
CAN slave logicCAN_SLAVE_TX, CAN_SLAVE_RX
CAN slave busCAN_SLAVE_H, CAN_SLAVE_L
DebugSWDIO, SWCLK, SWO, NRST
Datasheets / Reference Designs to Use Before Component Addition
Required before schematic capture:
  1. STMicroelectronics STM32F427ZI datasheet and reference manual hardware-design guidance.
  2. ST reference schematic for STM32F4 144-pin designs, where available.
  3. Microchip KSZ8895 datasheet and reference/evaluation board schematic for selected exact variant.
  4. Selected RJ45 integrated-magnetics connector datasheet.
  5. TI ISO1042 datasheet.
  6. TI ISO1042DWEVM schematic/user guide.
  7. Selected isolated 5V DC/DC module datasheet.
  8. Selected 3.3V regulator datasheet.
Implementation Order After User Approval
  1. Source/confirm suitable common Flux library parts for STM32F427ZI, KSZ8895 variant, ISO1042, non-isolated CAN transceiver, integrated-magnetics RJ45, RJ45 CAN connector, 3.3V regulator, isolated 5V DC/DC, crystals, ESD/protection parts, and passives.
  2. Add Step 1 power rails and regulators.
  3. Add STM32 core with clocks, reset, BOOT straps, SWD, and decoupling.
  4. Add KSZ8895 Ethernet switch support circuit.
  5. Add four RJ45 integrated-magnetics Ethernet ports and Ethernet protection.
  6. Add one non-isolated master CAN circuit, one ISO1042 isolated slave CAN circuit, isolated 5V supply, CAN protection, RJ45 connectors, and termination.
  7. Wire Step 1 nets using the net naming above.
  8. Run schematic ERC/design review.
  9. Fix ERC issues.
  10. Produce a Step 1 review summary and updated open-items list before moving to Step 2.
Verification Checklist Before Step 1 Is Considered Complete
  • STM32 all power pins connected and decoupled.
  • STM32 boot/reset/debug circuits present.
  • STM32 HSE/LSE clock circuits present or documented alternative chosen.
  • 3.3V regulator sized for STM32 + KSZ8895 + ISO1042 logic-side load.
  • KSZ8895 exact variant power rails match datasheet.
  • STM32 ↔ KSZ8895 RMII signals complete.
  • RMII 50MHz clock source is valid for both STM32 and KSZ8895.
  • Four Ethernet RJ45 integrated-magnetics ports connected per reference design.
  • Ethernet ESD/shield strategy documented.
  • One non-isolated master CAN channel implemented.
  • One ISO1042 isolated slave CAN channel implemented.
  • Isolated 5V generated locally from J8 5V and connected to ISO1042 isolated side.
  • GND and GND_CAN_ISO are not shorted.
  • CAN RJ45 pinout matches user decision: pin 1 CAN_H, pin 2 CAN_L, pin 3 GND.
  • Master CAN has 120Ω termination and uses main board GND.
  • Slave CAN has no termination and uses isolated GND_CAN_ISO.
  • CAN bus TVS protection present.
  • Test points added for bring-up rails and critical signals.
  • ERC/design review passes or remaining issues are documented.
Approval Questions Before Adding Components
  1. Confirmed: only slave CAN is isolated; master CAN is non-isolated.
  2. Confirmed: use 5V from J8 for Step 1 power input.
  3. Should the STM32 HSE remain 8MHz, or should we choose the clocking after confirming the KSZ8895/RMII 50MHz reference-clock plan?
  4. Confirmed: use suitable common Flux/library parts during implementation where exact MPN is not specified.
Status
Status: ready for user review. No components have been added yet.

  • Purpose

  • Confirmed User Decisions

  • Step 1 Functional Block Diagram

  • Schematic Pages / Functional Sections

  • Sheet 1 — Step 1 Power Entry and Local Rails

  • Sheet 2 — STM32F427ZI Core

  • Sheet 3 — KSZ8895 Ethernet Switch

  • Sheet 4 — CAN Interfaces

  • Sheet 5 — Connectors, Test Points, and Bring-Up Aids

  • Proposed Net Naming

  • Datasheets / Reference Designs to Use Before Component Addition

  • Implementation Order After User Approval

  • Verification Checklist Before Step 1 Is Considered Complete

  • Approval Questions Before Adding Components

  • Status