The completion executor finished its correction/routing pass. Before that pass, I confirmed the board was 65 × 56.5 mm but had an out-of-bounds Pi header, overlapping copper, severe congestion, and 19 unrouted connections.
Remaining
Independently inspect the executor’s final placement and routing
Re-run ERC/DRC to confirm zero airwires, overlaps, and out-of-bounds parts
Verify Pi 3B+ header and mounting-hole geometry
I can’t perform those final checks because no ACUs are currently available.
Received notification from "Raspberry Pi HAT PCB" that it finished — picking the work back up.
The Raspberry Pi HAT PCB executor reports the correction/routing pass completed, but I cannot independently inspect or reconcile the resulting board because the account currently has no available ACUs.
Still required before fabrication:
Re-run ERC/DRC and confirm zero airwires, shorts, overlaps, and out-of-bounds items
Purpose: Raspberry Pi Model 3B+ HAT that provides three independent, 5 V logic-level WS281x data outputs while keeping high-current LED power external.
Intended Use
A beginner-friendly replacement for a breadboard controller. The HAT plugs onto the Pi's 40-pin header and exposes pluggable terminals for two 12 V WS2811 FCOB strips and one 5 V WS2812 ring. This revision is schematic-complete and intended for later HAT PCB layout.
What the Device Should Do
Control two full 5 m BTF-LIGHTING 12 V WS2811 FCOB strips independently.
Control one 24-pixel 5 V WS2812 5050 ring independently.
Translate the Pi's 3.3 V GPIO signals to 5 V logic with an SN74AHCT125N.
Share ground among the Pi and all three external LED supplies.
Prevent either 12 V strip supply from entering the HAT.
Keep the external ring 5 V rail isolated from the Pi 5 V rail to prevent back-powering.
Main Features
Standard non-stacking 2x20 female Raspberry Pi HAT header.
Three buffered LED data outputs with 68 Ω source-series damping.
One PESD5V0S1BA bidirectional TVS diode per exposed data line.
100 nF local U1 decoupling plus 10 µF Pi-5-V logic bulk capacitance.
470 µF bulk capacitance on the separate external ring 5 V rail.
Through-hole pluggable terminal connectors where practical.
System Architecture
Text
Pi GPIO18 / PWM0 ----> AHCT ch1 -> 68R -> ESD -> J2 DATA/GND -> Strip 1 DIN/GND
Pi GPIO13 / PWM1 ----> AHCT ch2 -> 68R -> ESD -> J3 DATA/GND -> Strip 2 DIN/GND
Pi GPIO10 / SPI0 MOSI -> AHCT ch3 -> 68R -> ESD -> J5 DATA/GND/5V -> WS2812 ring
Pi 5V -------------> U1 VCC + C1/C2 only
Ring 5V adapter -> J4 -> RING_5V_EXT + C3 -> J5 -> ring
All grounds ----------------------------------------> common GND
12 V adapters -> strips directly; no 12 V terminal or net exists on HAT
Hardware Subsystems
Raspberry Pi Interface
J1: Adafruit 2222 2x20 female HAT header.
Both Pi 5 V header pins feed only PI_5V_LOGIC.
All Pi ground pins join the common GND reference.
Unused Pi GPIO/header pins remain pass-through/unconnected and are not marked no-connect.
Level Shifting
U1: Texas Instruments SN74AHCT125N, PDIP-14.
VCC operating range is 4.5–5.5 V; TTL-compatible VIH minimum is 2.0 V, so Pi 3.3 V logic is valid.
Channels 1–3: active-low OE tied to GND and data inputs driven by GPIO18, GPIO13, and GPIO10.
Channel 4: input tied to GND, OE tied to PI_5V_LOGIC, output marked no-connect; this safely disables the unused channel.
Output Conditioning and Protection
R1–R3: 68 Ω, axial through-hole, located electrically between buffer output and connector. 68 Ω is within the common 33–100 Ω range and limits edge-rate/ringing without materially degrading the 800 kHz waveform.
D1–D3: Nexperia PESD5V0S1BA, 5 V bidirectional TVS, from the connector-side data net to GND.
Power Separation
PI_5V_LOGIC: Pi-derived 5 V for U1 and C1/C2 only.
RING_5V_EXT: ring adapter input through J4 to J5 and C3 only.
No electrical connection exists between PI_5V_LOGIC and RING_5V_EXT.
No 12 V connector, net, or component exists on the HAT.
Interfaces and Connections
Table
Connector
Pin
Net / Label
User connection
J1
physical 12
PI_GPIO18_PWM0
PWM channel 0 data source
J1
physical 33
PI_GPIO13_PWM1
PWM channel 1 data source
J1
physical 19
PI_GPIO10_SPI0_MOSI
SPI data source
J2
1
STRIP1_DATA_5V
Strip 1 DIN only
J2
2
GND
Strip 1 ground reference
J3
1
STRIP2_DATA_5V
Strip 2 DIN only
J3
2
GND
Strip 2 ground reference
J4
1
RING_5V_EXT
Regulated external 5 V adapter positive input
J4
2
GND
Ring adapter negative/ground input
J5
1
RING_5V_EXT
Ring +5 V output
J5
2
GND
Ring ground output
J5
3
RING_DATA_5V
Ring DIN output
Wiring warning: Never connect either 12 V adapter positive lead to J2, J3, J4, or J5. Strip 12 V power goes directly from each 12 V/10 A adapter to its strip. Only strip DIN and GND connect to J2/J3.
Power and Runtime Expectations
Raspberry Pi: powered independently by its own regulated 5 V supply; HAT does not power the Pi.
Strip 1: independent 12 V/10 A adapter connected directly to strip power conductors.
Strip 2: independent 12 V/10 A adapter connected directly to strip power conductors.
Ring: independent regulated 5 V adapter connected at J4; recommend at least 2 A continuous capability.
Power Tree and Power Budget
Table
Source / rail
Load carried by HAT
Estimated worst case
Notes
Pi 5 V -> PI_5V_LOGIC
SN74AHCT125 + dynamic LED data drive
RING_5V_EXT
24 × WS2812 pixels
Strip 1 12 V adapter
Full 5 m strip
Up to adapter/strip demand, external to HAT
12 V bypasses PCB completely
Strip 2 12 V adapter
Full 5 m strip
Up to adapter/strip demand, external to HAT
12 V bypasses PCB completely
The HAT ground path between J4 and J5 carries the ring return current and must be sized for at least 1.5 A continuous in PCB layout. J2/J3 ground conductors are signal references only and must not be used as strip power-return wiring.
Firmware-Relevant Hardware Requirements
Table
Output
BCM GPIO
Physical pin
Peripheral
Notes
Strip 1
18
12
PWM0
rpi_ws281x-supported PWM output
Strip 2
13
33
PWM1
second rpi_ws281x PWM channel
Ring
10
19
SPI0 MOSI
dedicated SPI LED waveform output
The rpi_ws281x PWM backend supports two independent PWM strings in one configured instance.
PWM use conflicts with Raspberry Pi onboard analog audio (snd_bcm2835); disable/blacklist that audio path or use USB/HDMI audio.
SPI0 must be enabled and dedicated to the ring; do not share SPI0 with another device.
On Raspberry Pi 3, fix core_freq=250 when using timing-sensitive SPI encoding.
Software must validate concurrent use of the dual-PWM backend and a separate SPI waveform driver. The hardware peripherals and pins are independent, but a single high-level library instance may not combine PWM and SPI backends. Recommended architecture: one rpi_ws281x instance for both PWM channels plus a dedicated SPI driver/process for the ring.
Avoid DMA channel 5 on Pi 3; rpi_ws281x documentation identifies DMA channel 10 as the customary safer default.
Manufacturing and Assembly Expectations
Beginner-friendly through-hole PDIP buffer, axial resistors, radial/disc capacitors, Pi socket header, and terminal blocks.
ESD diodes are SOD-323 SMD because a compact suitable library part is available.
Later layout must use HAT mechanical dimensions, keep connectors accessible at board edges, place C1 adjacent to U1 VCC/GND, place R1–R3 near U1 outputs, and place D1–D3 near external connectors.
Physical Design Expectations
HAT may cover the Pi GPIO area completely.
Use a Raspberry Pi HAT-compatible outline and mounting holes during PCB layout.
Clearly mark STRIP 1 DATA/GND, STRIP 2 DATA/GND, RING 5V IN, and RING 5V/GND/DATA on silkscreen.
Add conspicuous NO 12V TO HAT silkscreen near J2/J3/J4/J5.
Important Design Decisions
AHCT rather than HC/HCT: guaranteed 2.0 V VIH at 5 V supply accepts Raspberry Pi 3.3 V outputs with margin.
Fixed-low OE on used channels matches the requirement and keeps the signal path simple.
Unused channel is disabled with OE high and input defined low.
Separate ring power net prevents Pi back-feed without adding a series diode voltage drop to the WS2812 ring.
68 Ω series resistors balance ringing reduction and edge integrity.
Assumptions and Open Risks
External adapters are regulated, correctly polarized, and share ground through the indicated connectors.
The two strips receive power injection appropriate to their length and manufacturer instructions; that high-current wiring is outside the HAT.
Ring connector current rating and PCB copper must be verified during layout for at least 1.5 A continuous.
Concurrent dual-PWM plus SPI software operation needs bench validation on the target Raspberry Pi OS/kernel/library versions.
ESD TVS clamping is intended for normal handling/cable ESD, not lightning or miswiring to 12 V.
Change Notes
Renamed project and set project description.
Added J1, U1, J2–J5, R1–R3, C1–C3, and D1–D3.
Implemented three named GPIO/data paths, common ground, separated Pi/ring 5 V rails, decoupling, bulk capacitance, output damping, and ESD protection.
Explicitly disabled U1 channel 4 and left unused Pi header pins unmarked.